Thanks for your answer.
The idea is not to model only the core, but the entire platform, to build a
complete virtual platform of the entire SoC.
I mean the virtual platform will include the core model and the
“peripherals” models like IRQ, Timer, UART, I2C, SPI, …
UART / I2C / SPI IP… should export a TLM interface for their protocol.
Then, these TLM interfaces could be connected to a backend for interaction.
(or potentially connected to real hardware for example)
As you said USB and PCIe could be really interesting and a good challenge.
It can be a part of the plan.
2016-03-15 16:35 GMT+01:00 Alex Bradbury <asb(a)asbradbury.org>:
On 13 March 2016 at 00:32, Guillaume Delbergue
> I’m a Ph.D student working on TLM standard and its application to non
memory mapped interfaces, and mainly about protocols used in SoC. I’m
interested in building a virtual platform for the lowRISC SoC based on the
SystemC IEEE standard.
> More and more project are developed using a top-down approach building
first TLM LT models, then maybe AT,... until the RTL. Virtual platforms
enable software developers to build drivers and test their code early using
a virtual version. They bring software and hardware team to enable early
software and early validation. As I can see, you’re talking in your "Plans
for RISC-V in 2016 » presentation about SPI, I2C, I2S, UART IP, I think it
would be interesting for the community to have a TLM LT level (for example)
equivalent to ease hardware, driver development and testing.
> What’s the interest of the community in such a project ? What about
having an open source virtual platform based on the industry standard (IEEE
> Let me know if you have any questions.
Hi Guillaume. Thanks for getting in touch. My personal experience with
SystemC is through our Loki research project where we found a model of
the complete design to be useful for rapidly iterating on hardware
designs and to verify against with the RTL implementation that
followed. I have less experience using models for IP blocks in
isolation - perhaps you could expand on how you feel a loosely timed
model of SPI, I2C, ... could be exploited by the community? Although
much more challenging, I wonder if models for higher speed protocols
like USB or PCIe might be interesting.