On 14 November 2016 at 19:13, Tobias Strauch <tobias(a)cloudx.cc> wrote:
I would like to use the lowRISC platform as a reference for some of my projects. I hope
that I can contribute back to the project one day.
Hi Tobias, thanks for kicking off the thread this week.
In the last weeks I tried to get a good internal understanding of the
Rocket core. Because I’m not a guy who loves to read documents, - rather doing it the hard
way – I converted a huge section of the Rocket chisel code into SystemVerilog code. I hope
I will summarize this experience one day.
Interesting - do you intend to share the SystemVerilog conversion? Are
you converting the chisel manually or doing some post-processing on
the generated Verilog?
The next step is to convert the lowRISC\Rocket design into a language
I’m working on (PDVL) and to verify it. For that I have two question, and it would be
great if someone replies if I’m missing something.
Q1: Are there documents available for Rocket and lowRISC other than:
I think that's all the available documentation currently, though I'm
sure Wei will chime in if there's anything else he knows of.
Q2: Are there functional verification environments available for
Rocket and lowRISC other than:
You might also be interested in Axe https://github.com/CTSRD-CHERI/axe
So what are you working on in this week of November?
We've been having ongoing discussions about further tagged memory
benchmarks and use cases, as well as the requirements for an initial
tagged memory rule table. I've continued work on adding codegen to the
RISC-V LLVM backend and have been doing some more Linux kernel
hacking, partly as a way of better familiarising myself with the finer
details of RISC-V's privileged spec.
I was recently in the US for the GSoC mentor's summit and the LLVM Dev
Meeting. I also caught up with various collaborators in the area. I'm
hoping we can make progress this week on sorting out some remaining
issues with the coreboot port to lowRISC (instantiated on FPGA) and
demonstrate coreboot loading a Linux payload on the Nexys4, probably
via an intermediate loader to load the kernel from SD card.