11:51 a.m.
It's a new month, so I figured we should make a new thread rather than
just replying to the old one.
What are you working on this week?
The funding application I was working on last week has ended up taking
an awful lot of time, and I still need to produce a short pitch video.
I think it has been useful in general though, giving me more time to
take a step back and think about the things I'd really like to see
lowRISC CIC achieve over the coming year and beyond.
I'm off to Bologna for ORConf <http://orconf.org/> on Thursday. I
imagine I'll spend a good chunk of Tuesday preparing and polishing my
talk. Otherwise:
1) I've been playing with Sagar's latest qemu-riscv work over the weekend
2) Wei's made great progress on his tagged memory software model, and
I hope to play a small supporting role by helping out with supplying
benchmarks and fiddly test cases
3) Continued riscv-llvm work
Best,
Alex
noon
It's a new academic year, so roll on a burst of productive activity.
Right now I am running the Chisel portion of the design through ASIC tools
to get area and performance estimates with the aim of preparing a viable
database by Christmas.
In addition the non-chisel design will require customizing to remove
Xilinx specific PHYs and IP.
Jonathan
On 03/10/16 08:51, Alex Bradbury wrote:
It's a new month, so I figured we should make a new thread rather
than
just replying to the old one.
What are you working on this week?
The funding application I was working on last week has ended up taking
an awful lot of time, and I still need to produce a short pitch video.
I think it has been useful in general though, giving me more time to
take a step back and think about the things I'd really like to see
lowRISC CIC achieve over the coming year and beyond.
I'm off to Bologna for ORConf <http://orconf.org/> on Thursday. I
imagine I'll spend a good chunk of Tuesday preparing and polishing my
talk. Otherwise:
1) I've been playing with Sagar's latest qemu-riscv work over the weekend
2) Wei's made great progress on his tagged memory software model, and
I hope to play a small supporting role by helping out with supplying
benchmarks and fiddly test cases
3) Continued riscv-llvm work
Best,
Alex
12:57 p.m.
Well, already mentioned by Alex, I have finished the coding part of
tagged memory support in Spike.
So this week I will generate some functional tests to debug the tagged
memory model.
Hopefully for the following weeks, I can get some performance tests from
Alex and explore some performance trade-offs.
-Wei
On 03/10/2016 09:00, Dr Jonathan Kimmitt wrote:
It's a new academic year, so roll on a burst of productive
activity.
Right now I am running the Chisel portion of the design through ASIC
tools
to get area and performance estimates with the aim of preparing a
viable database by Christmas.
In addition the non-chisel design will require customizing to remove
Xilinx specific PHYs and IP.
Jonathan
On 03/10/16 08:51, Alex Bradbury wrote:
> It's a new month, so I figured we should make a new thread rather than
> just replying to the old one.
>
> What are you working on this week?
>
> The funding application I was working on last week has ended up taking
> an awful lot of time, and I still need to produce a short pitch video.
> I think it has been useful in general though, giving me more time to
> take a step back and think about the things I'd really like to see
> lowRISC CIC achieve over the coming year and beyond.
>
> I'm off to Bologna for ORConf <http://orconf.org/> on Thursday. I
> imagine I'll spend a good chunk of Tuesday preparing and polishing my
> talk. Otherwise:
> 1) I've been playing with Sagar's latest qemu-riscv work over the
> weekend
> 2) Wei's made great progress on his tagged memory software model, and
> I hope to play a small supporting role by helping out with supplying
> benchmarks and fiddly test cases
> 3) Continued riscv-llvm work
>
> Best,
>
> Alex
>
2:18 a.m.
On Mon, Oct 3, 2016 at 7:57 PM, Wei Song <ws327(a)cam.ac.uk> wrote:
Well, already mentioned by Alex, I have finished the coding part of
tagged memory support in Spike.
Great work! Is it based on 1.9 branch?
So this week I will generate some functional tests to debug the
tagged
memory model.
Hopefully for the following weeks, I can get some performance tests from
Alex and explore some performance trade-offs.
-Wei
On 03/10/2016 09:00, Dr Jonathan Kimmitt wrote:
> It's a new academic year, so roll on a burst of productive activity.
>
> Right now I am running the Chisel portion of the design through ASIC
> tools
>
> to get area and performance estimates with the aim of preparing a
> viable database by Christmas.
>
> In addition the non-chisel design will require customizing to remove
> Xilinx specific PHYs and IP.
>
> Jonathan
>
> On 03/10/16 08:51, Alex Bradbury wrote:
>> It's a new month, so I figured we should make a new thread rather than
>> just replying to the old one.
>>
>> What are you working on this week?
>>
>> The funding application I was working on last week has ended up taking
>> an awful lot of time, and I still need to produce a short pitch video.
>> I think it has been useful in general though, giving me more time to
>> take a step back and think about the things I'd really like to see
>> lowRISC CIC achieve over the coming year and beyond.
>>
>> I'm off to Bologna for ORConf <http://orconf.org/> on Thursday. I
>> imagine I'll spend a good chunk of Tuesday preparing and polishing my
>> talk. Otherwise:
>> 1) I've been playing with Sagar's latest qemu-riscv work over the
>> weekend
>> 2) Wei's made great progress on his tagged memory software model, and
>> I hope to play a small supporting role by helping out with supplying
>> benchmarks and fiddly test cases
>> 3) Continued riscv-llvm work
>>
>> Best,
>>
>> Alex
>>
>
>
--
Hesham
3:39 p.m.
On 03/10/2016 23:18, Hesham Almatary wrote:
On Mon, Oct 3, 2016 at 7:57 PM, Wei Song <ws327(a)cam.ac.uk>
wrote:
> Well, already mentioned by Alex, I have finished the coding part of
> tagged memory support in Spike.
Great work! Is it based on 1.9 branch?
No. I am working on an old version of spike which matches with the
Rocket cores used by the current lowRISC hardware implementation.
Although I do plan to have a merge later this year to bring the lowRISC
Rocket cores up to date with ucb-bar.
-Wei
11:58 p.m.
On Mon, Oct 03, 2016 at 08:51:55AM +0100, Alex Bradbury wrote:
What are you working on this week?
Last week I haven't had much time but I managed to get PV6 to start without
any help on its own page tables. Most is not implemented so no demo yet folks!
Implementing it, I was confronted with assumptions in the PV6 kernel that I
didn't account for; one of it be that all physical memory needs to be mapped
1:1 in the kernel space. Oh well.
So for this week, if I manage to get some time, is to try to implement some
beginnings of the hypervisor interface I designed and basically redo my work
from last week :-/ The choice has been to either go for PV6 on an (nearly)
unmodified Spike first and then changing it to my hypervisor idea or to go
directly to my idea implementing both Spike and PV6 simultaneously.
I'm off to Bologna for ORConf <http://orconf.org/> on
Thursday. I
imagine I'll spend a good chunk of Tuesday preparing and polishing my
talk. Otherwise:
:'( Won't be there this year. Hopefully next year will be better. If all goes
well I'll have much more time to hack^Wwork in say a month time...
I've been following the isa-dev's story on hypervisors and the SEE with
interest. Nice to see other ppls ideas on it though I am not sure I share
their ideas.
2) Wei's made great progress on his tagged memory software model,
and
I hope to play a small supporting role by helping out with supplying
benchmarks and fiddly test cases
Nice! I presume its the 2 bit model with the separate instructions like
before? Has you looked in my PUMP-lite proposal Wei?
Have a good week,
Reinoud
2:18 p.m.
On 04/10/2016 20:58, Reinoud Zandijk wrote:
> 2) Wei's made great progress on his tagged memory software model, and
> I hope to play a small supporting role by helping out with supplying
> benchmarks and fiddly test cases
Nice! I presume its the 2 bit model with the separate instructions like
before? Has you looked in my PUMP-lite proposal Wei?
Currently I am more on how to implement the tag cache efficiently rather
than the general use cases of tags.
You might like to point the proposal to me again.
-Wei
3:39 p.m.
Hi Wei,
On Wed, Oct 05, 2016 at 11:18:01AM +0100, Wei Song wrote:
On 04/10/2016 20:58, Reinoud Zandijk wrote:
>> 2) Wei's made great progress on his tagged memory software model, and
>> I hope to play a small supporting role by helping out with supplying
>> benchmarks and fiddly test cases
> Nice! I presume its the 2 bit model with the separate instructions like
> before? Has you looked in my PUMP-lite proposal Wei?
Currently I am more on how to implement the tag cache efficiently rather
than the general use cases of tags.
You might like to point the proposal to me again.
I've attached the latest version to this message :)
Reinoud
3:35 p.m.
On 3 October 2016 at 08:51, Alex Bradbury <asb(a)asbradbury.org> wrote:
It's a new month, so I figured we should make a new thread rather
than
just replying to the old one.
What are you working on this week?
I'm travelling back from Bologna today after an excellent ORCONF
<http://orconf.org/>;. Major credit to the organisers for another
instalment of such an important event for the open source digital
design community.
Due to travelling I lack an internet connection that doesn't block
SSH, which is limiting what I can do today (this weeks' LLVM Weekly
will appear later today after I'm back in the UK, but is slightly
delayed from the normal release time due to the lack of SSH).
I refreshed the initial RISC-V LLVM patches over the weekend and have
posted a status update
<http://lists.llvm.org/pipermail/llvm-dev/2016-October/105768.html>
which may be of interest.
This week I'll be continuing riscv-llvm work, preparing for a lowRISC
project meeting, and hopefully look at benchmarking+testing for Wei's
implementation of tagged memory which I didn't get round to last week.
Happy hacking,
Alex
3:57 p.m.
On 10/10/2016 12:35, Alex Bradbury wrote:
This week I'll be continuing riscv-llvm work, preparing for a
lowRISC
project meeting, and hopefully look at benchmarking+testing for Wei's
implementation of tagged memory which I didn't get round to last week.
Good to know. The tagged spike passed my random tests last week.
In the meanwhile, I am trying to figure out an X state issue reported by
Jonathan which seems escaped from Verilator simulations for a long time
due to its limited capability in simulating 4-state signals.
-Wei
12:20 p.m.
Hi all,
got back home from ORCONF and one month of paternal leave. I doubt I
will find too much time this week, but one of the main things on my TODO
list is planning what to do debug-wise until the end of the year
(hardening, infrastructure, features).
Have a great week!
Cheers,
Stefan
1:07 p.m.
On 11 October 2016 at 09:20, Stefan Wallentowitz <stefan(a)wallentowitz.de> wrote:
Hi all,
got back home from ORCONF and one month of paternal leave. I doubt I
will find too much time this week, but one of the main things on my TODO
list is planning what to do debug-wise until the end of the year
(hardening, infrastructure, features).
We should really stay synced up with Philipp's work too (by we, I mean
the lowRISC team in Cambridge - I imagine you're fairly well
synchronised). We're definitely thinking along very similar lines to
the 'diagnosis processor' or potentially more specialised versions of
it.
Enjoy your paternal leave!
Alex
12:04 a.m.
On 3 October 2016 at 08:51, Alex Bradbury <asb(a)asbradbury.org> wrote:
It's a new month, so I figured we should make a new thread rather
than
just replying to the old one.
What are you working on this week?
Somehow it's another week already.
I've been doing some more QEMU and Linux kernel exploration/hacking.
The initial RISC-V LLVM patches are inching ever close to being
merged. I've also been doing some planning of my future work, which as
you may have seen led to this tool
http://www.lowrisc.org/blog/2016/10/generating-a-gantt-chart-from-hjson-i....
As they always say, you know you're reaching peak productivity when
you start building your own planning tools. Or was that
procrastination?
Have a good week everyone!
Alex
1:18 p.m.
On 17/10/2016 21:04, Alex Bradbury wrote:
On 3 October 2016 at 08:51, Alex Bradbury <asb(a)asbradbury.org>
wrote:
> It's a new month, so I figured we should make a new thread rather than
> just replying to the old one.
>
> What are you working on this week?
>
As an early preparation for the next release, I begin to look for a
major merge of the updates from ucb-bar/rocket-chip.
So far I have noticed that the chip top-level had been significantly
refactored with deeper encapsulation that parameters related to certain
components are enclosed in those components. The TileLink on-chip
interconnects are gradually replaced by a new TileLink2. This TileLink2
also introduces a new lazy module methodology which leads to module
declaration in factory classes rather than normal module classes.
Generally I appreciate all the efforts from Berkeley/SiFive to make the
whole rocket-chip more modularized however I must admit the learning
curve for anyone who would like to further develop the Chisel
implementation rather than just use it out-of-box becomes even more
steep. Right now I am buried in the new implementations of TileLink2 and
endeavor to figure out the newly defined communication infrastructure.
According to the commit log the TileLink2 is still in its early stage,
considering the refactor happens only less than 2 months ago.
-Wei
12:29 a.m.
On Mon, Oct 17, 2016 at 09:04:49PM +0100, Alex Bradbury wrote:
On 3 October 2016 at 08:51, Alex Bradbury <asb(a)asbradbury.org>
wrote:
> It's a new month, so I figured we should make a new thread rather than
> just replying to the old one.
>
> What are you working on this week?
Somehow it's another week already.
Ditto here. I've been ill so haven't managed to do much. I now have PV6
booting into its own pagetables (again) using a console and a communication
channel to an emulated `hardware hypervisor' in Spike.
Not really that exiting I know but its a start. PV6 isn't as far as I had
hoped and much of the effort will be in porting PV6 :-/ not in trying out my
hypervisor ideas!
Anyway, I'll see what I can do. What annoys me most is that the code uses
concepts like `char` `uint' and `ulong' instead of say uint8_t, uint32_t or
uint64_t or the like. Bummer but to search and replace all ? nah, I'd spend
more time debugging my own mistakes than debugging code :-D
Anyway, I'll see what I can do this week.
Cheers,
Reinoud
2:05 p.m.
On 3 October 2016 at 08:51, Alex Bradbury <asb(a)asbradbury.org> wrote:
It's a new month, so I figured we should make a new thread rather
than
just replying to the old one.
What are you working on this week?
It's the last full week of October. I'm flying out to the US on
Thursday (it's the Google Summer of Code Mentor Summit over the
weekend, then I've got various meetings and finally it's the LLVM
Developers Meeting on Thu/Fri). I'm spending some time getting
everything sorted for the trip. I ended up spending some time getting
more familiar with the Linux kernel last week, though suspect I'll be
focusing primarily on LLVM in the time I have for hacking this week.
What's everyone else working on?
Best,
Alex
2:11 p.m.
Just now I am investigating timing and area performance of various
Rocket core
configurations, with the eventual aim of producing a database of lowRISC RTL
ready to go to silicon.
On 10/25/2016 11:05 AM, Alex Bradbury wrote:
On 3 October 2016 at 08:51, Alex Bradbury <asb(a)asbradbury.org>
wrote:
> It's a new month, so I figured we should make a new thread rather than
> just replying to the old one.
>
> What are you working on this week?
It's the last full week of October. I'm flying out to the US on
Thursday (it's the Google Summer of Code Mentor Summit over the
weekend, then I've got various meetings and finally it's the LLVM
Developers Meeting on Thu/Fri). I'm spending some time getting
everything sorted for the trip. I ended up spending some time getting
more familiar with the Linux kernel last week, though suspect I'll be
focusing primarily on LLVM in the time I have for hacking this week.
What's everyone else working on?
Best,
Alex
6:53 p.m.
On Tue, Oct 25, 2016 at 11:05:37AM +0100, Alex Bradbury wrote:
> What are you working on this week?
A few weekends ago, we had a coreboot developer conference in Berlin,
where we first booted coreboot on lowRISC running on the Nexys4 DDR (by
loading it into RAM from the µSD card, but that's currently also
necessary for spike). The support code for this board[1] along with
some refactoring[2] of the RISC-V code is slowly being merged upstream.
Greetings,
Jonathan Neuschäfer
[1]: https://review.coreboot.org/#/c/17132/
[2]:
https://review.coreboot.org/#/q/status:merged+topic:riscv+after:2016-08-1...
9:40 p.m.
On 26 October 2016 at 15:53, Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> wrote:
On Tue, Oct 25, 2016 at 11:05:37AM +0100, Alex Bradbury wrote:
> > What are you working on this week?
A few weekends ago, we had a coreboot developer conference in Berlin,
where we first booted coreboot on lowRISC running on the Nexys4 DDR (by
loading it into RAM from the µSD card, but that's currently also
necessary for spike). The support code for this board[1] along with
some refactoring[2] of the RISC-V code is slowly being merged upstream.
That's absolutely fantastic news, congratulations!
Thanks for sharing,
Alex
2348
days inactive
2371
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18 comments
7 participants
participants (7)
-
Alex Bradbury -
Dr Jonathan Kimmitt -
Hesham Almatary -
Jonathan Neuschäfer -
Reinoud Zandijk -
Stefan Wallentowitz -
Wei Song