8:28 p.m.
Hi Alex,
I understand. There is a lot to do and I guess one of the primary goals with FPGA is
verification so that would kind of focus the effort. The same question applies to
integration for other Xilinx IP (thinking about Ethernet).
I would be interested to try myself but my time is also limited and I need time to learn
Chisel.
I'm currently trying to get a PoC of /another/ software simulation of RISC-V for
security mitigation research. I was thinking of basing it on Spike but decided to go down
another path with an alternative design. I'm working on the new 1.9 priv spec and am
implementing the tagged TLB, caches and page walker. Interrupts are a way off... and the
spec is getting bigger...
Cheers,
Michael.
Sent from my iPhone
On 1/08/2016, at 9:23 PM, Alex Bradbury <asb(a)asbradbury.org>
wrote:
We discussed this idea with Ron Minnich some while back, and I really
like it. For now it's not a high priority, and as Wei says we have to
be very selective about where we put our development effort - it's
definitely something I'd like to see though, and we'd be happy to
advise anyone who wanted to have a go at implementing it.
Best,
Alex
8:32 p.m.
New subject: Memory-mapped SPI flash on Nexys4?
On 1 August 2016 at 12:28, Michael Clark <michaeljclark(a)mac.com> wrote:
I'm currently trying to get a PoC of /another/ software
simulation of RISC-V
for security mitigation research. I was thinking of basing it on Spike but
decided to go down another path with an alternative design. I'm working on
the new 1.9 priv spec and am implementing the tagged TLB, caches and page
walker. Interrupts are a way off... and the spec is getting bigger...
I've been following your work with keen interest. High performance DBT
for RISC-V is a really exciting goal.
Best,
Alex
6:04 p.m.
New subject: Memory-mapped SPI flash on Nexys4?
On 1/08/2016, at 11:32 PM, Alex Bradbury <asb(a)asbradbury.org>
wrote:
> On 1 August 2016 at 12:28, Michael Clark <michaeljclark(a)mac.com> wrote:
> I'm currently trying to get a PoC of /another/ software simulation of RISC-V
> for security mitigation research. I was thinking of basing it on Spike but
> decided to go down another path with an alternative design. I'm working on
> the new 1.9 priv spec and am implementing the tagged TLB, caches and page
> walker. Interrupts are a way off... and the spec is getting bigger...
I've been following your work with keen interest. High performance DBT
for RISC-V is a really exciting goal.
Thanks for the feedback!
It's all pretty exciting. I'd be excited if I was asked to help with a Debian port
but I don't think I would have time. Pretty much excited by anything.
I need to get priv mode running so I can try interop with lowRISC. This excites me the
most. Diverse implementations of a standard should create a great foundation for research.
Hopefully we don't fragment. The boot stuff is contentious but I like where it is
heading (bbl and ELF).
I wish I could work faster. I am undeterred but I have underestimated how much effort it
is. It's both a time risk and we don't know the performance of hopefully a near
optimal monomorphism. Could keep busy for a long time. Lots of ideas. Grouping and packing
the scalar ISA into SIMD AVX (I'm not aiming that high in the short to medium term
without finding collaborators).
QEMU exists now which is good for the community and there are other useful byproducts from
having another initiative. Morphing the translation was one of them (in Open Source).
Cheers,
Michael
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