I understand. There is a lot to do and I guess one of the primary goals with FPGA is
verification so that would kind of focus the effort. The same question applies to
integration for other Xilinx IP (thinking about Ethernet).
I would be interested to try myself but my time is also limited and I need time to learn
I'm currently trying to get a PoC of /another/ software simulation of RISC-V for
security mitigation research. I was thinking of basing it on Spike but decided to go down
another path with an alternative design. I'm working on the new 1.9 priv spec and am
implementing the tagged TLB, caches and page walker. Interrupts are a way off... and the
spec is getting bigger...
Sent from my iPhone
On 1/08/2016, at 9:23 PM, Alex Bradbury <asb(a)asbradbury.org>
We discussed this idea with Ron Minnich some while back, and I really
like it. For now it's not a high priority, and as Wei says we have to
be very selective about where we put our development effort - it's
definitely something I'd like to see though, and we'd be happy to
advise anyone who wanted to have a go at implementing it.