The target board for the minion-v0.4 release is Nexys-4DDR. We had to cut out some
optional features for this board. Unfortunately the next low cost board in the same
series, the Nexys-Video, lacks flow control on its UART, which causes problems for the
trace debugger. Our build system in principle supports SMP rocket systems that share
L2-cache and DDR memory, coherence is managed by TileLink. I don't think anybody has
built it for FPGA recently.
LowRISC team member
Sent from my iPhone
On 30 May 2017, at 17:33, Tobias Strauch <tobias(a)cloudx.cc>
may I add a question to the one below:
3) I know it has mentioned a few months ago, but what would be the target virtex eval
board for the next lowrisc release. maybe Wei mentioned it (and the questions below) at
the WS, but the sound is terrible.
thank you for your answer in adcance, see you in Hebden Bridge, cheers, Tobias
> Tobias Strauch <tobias(a)cloudx.cc> hat am 17. April 2017 um 12:39 geschrieben:
> Hi Rob et al.,
> thank you for sharing an update on your wonderful project at the RISC-V WS in
> I’ve been following the lowRISC project closely and I was wondering, if I may ask you
> 1) Support for (many) MultiCores (except the Minions):
> Are you still planning to go for a solution, that supports multiple cores of the same
kind (except the Minion Cores Network), so let’s say, multiple rockets, multiple BOOMs
etc. I’m particular interested in how you solve the cache coherence\software\OS software
problems that come with it.
> 2) Minions and local memory
> Will you attach local memory to the individual minions, and if so, how will your
global memory hierarchy look like?
> Thank you so much in advance for your answers.
> Cheers, Tobias
> PS: Can’t wait to work with your next release.
> PPS: I think the survey on the RISC-V cores you mentioned is highly appreciated.