6:28 p.m.
Dear all,
I wanted to simulate lowRISC untether-v0.2 using verilator as described in
http://www.lowrisc.org/docs/untether-v0.2/vsim/
System Config:
Ubuntu 16.04
Intel i5
Verilator V3.920
Following is the sequence of commands used:
$cd lowrisc-chip
$source set_riscv_env.sh
$cd vsim
$export VERILATOR_ROOT=/path/to/verilator/root/directory
$make sim
$make run-asm-tests
runs successfully
$make run-bmarks-test
fails with the following terminal output:
./DefaultConfig-sim +max-cycles=100000000 +load=output/towers.riscv.hex |
/home/anshujit/work/lowrisc-chip/riscv/bin/spike-dasm >
output/towers.riscv.verilator.out && [ $PIPESTATUS -eq 0 ]
Core 0 get unsolved tohost code 21680
Makefile:201: recipe for target 'output/towers.riscv.verilator.out' failed
make: *** [output/towers.riscv.verilator.out] Error 1
Kindly, let me know how to debug this problem.
--
With Regards
Anshujit Sharma
Research Assistant
Computer Aided Design Laboratory
Department of Computational and Data Sciences <http://cds.iisc.ac.in/>
Indian Institute of Science
Bangalore: 560012, India
Tel: +918011223483, +917406490246
email: anshujit(a)cadl.iisc.ernet.in, anshujitsharma(a)gmail.com
7:17 p.m.
Dear Anshujit,
This is a very old release and a number of improvements and bug fixes
have been made since then. You may find it profitable to compile the
benchmark under Linux in the latest release , this will give a more
helpful error message.
Regards,
Jonathan
On 13/03/18 09:28, Anshujit Sharma wrote:
Dear all,
I wanted to simulate lowRISC untether-v0.2 using verilator as described in
http://www.lowrisc.org/docs/untether-v0.2/vsim/
System Config:
Ubuntu 16.04
Intel i5
Verilator V3.920
Following is the sequence of commands used:
$cd lowrisc-chip
$source set_riscv_env.sh
$cd vsim
$export VERILATOR_ROOT=/path/to/verilator/root/directory
$make sim
$make run-asm-tests
runs successfully
$make run-bmarks-test
fails with the following terminal output:
./DefaultConfig-sim +max-cycles=100000000 +load=output/towers.riscv.hex |
/home/anshujit/work/lowrisc-chip/riscv/bin/spike-dasm >
output/towers.riscv.verilator.out && [ $PIPESTATUS -eq 0 ]
Core 0 get unsolved tohost code 21680
Makefile:201: recipe for target 'output/towers.riscv.verilator.out' failed
make: *** [output/towers.riscv.verilator.out] Error 1
Kindly, let me know how to debug this problem.
8:16 p.m.
Thank you Sir for your reply.
I moved to the ethernet-v0.5 branch and rebuilt the riscv-tools. Here again
I faced some issues with run-bmark-tests.
Following is the sequence of commands used:
$cd ethernet-v0.5
$source set_riscv_env.sh
$cd vsim
$export VERILATOR_ROOT=/path/to/verilator/root/directory
$make sim
$make run-asm-tests
runs successfully
$make run-bmarks-test
fails with the following terminal output:
mkdir -p ./output
make -C ./riscv-tests/benchmarks median
make[1]: Entering directory
'/home/anshujit/work/ethernet-v0.5/vsim/riscv-tests/benchmarks'
cc median.o -o median
/usr/bin/ld: cannot open output file median: Is a directory
collect2: error: ld returned 1 exit status
<builtin>: recipe for target 'median' failed
make[1]: *** [median] Error 1
make[1]: Leaving directory
'/home/anshujit/work/ethernet-v0.5/vsim/riscv-tests/benchmarks'
Makefile:269: recipe for target 'output/median.riscv' failed
make: *** [output/median.riscv] Error 2
On Tue, Mar 13, 2018 at 3:47 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk>
wrote:
Dear Anshujit,
This is a very old release and a number of improvements and bug fixes have
been made since then. You may find it profitable to compile the benchmark
under Linux in the latest release , this will give a more helpful error
message.
Regards,
Jonathan
On 13/03/18 09:28, Anshujit Sharma wrote:
> Dear all,
>
> I wanted to simulate lowRISC untether-v0.2 using verilator as described in
> http://www.lowrisc.org/docs/untether-v0.2/vsim/
>
> System Config:
> Ubuntu 16.04
> Intel i5
> Verilator V3.920
>
> Following is the sequence of commands used:
> $cd lowrisc-chip
> $source set_riscv_env.sh
> $cd vsim
> $export VERILATOR_ROOT=/path/to/verilator/root/directory
> $make sim
>
> $make run-asm-tests
> runs successfully
>
> $make run-bmarks-test
> fails with the following terminal output:
>
> ./DefaultConfig-sim +max-cycles=100000000 +load=output/towers.riscv.hex |
> /home/anshujit/work/lowrisc-chip/riscv/bin/spike-dasm >
> output/towers.riscv.verilator.out && [ $PIPESTATUS -eq 0 ]
> Core 0 get unsolved tohost code 21680
> Makefile:201: recipe for target 'output/towers.riscv.verilator.out'
> failed
> make: *** [output/towers.riscv.verilator.out] Error 1
>
> Kindly, let me know how to debug this problem.
>
>
>
--
With Regards
Anshujit Sharma
Research Assistant
Computer Aided Design Laboratory
Department of Computational and Data Sciences <http://cds.iisc.ac.in/>
Indian Institute of Science
Bangalore: 560012, India
Tel: +918011223483, +917406490246
email: anshujit(a)cadl.iisc.ernet.in, anshujitsharma(a)gmail.com
9 p.m.
The benchmark tests from the original Rocket-Chip rely on the
host-interface (debugger in latest versions) for IO stream and file support.
lowRISC SoC is untethered; therefore, there is no direct support for
these functions in the bare-metal mode.
It is actually supposed to fail due to these reasons.
As for the ethernet-v0.5 branch, the error seems like the Makefile does
not match with the directory.
However, as I said in the previous paragraph, 'make run-bmark-tests'
does not work out of the box even the Make file is fixed.
-Wei
On 13/03/18 19:16, Anshujit Sharma wrote:
Thank you Sir for your reply.
I moved to the ethernet-v0.5 branch and rebuilt the riscv-tools. Here again
I faced some issues with run-bmark-tests.
Following is the sequence of commands used:
$cd ethernet-v0.5
$source set_riscv_env.sh
$cd vsim
$export VERILATOR_ROOT=/path/to/verilator/root/directory
$make sim
$make run-asm-tests
runs successfully
$make run-bmarks-test
fails with the following terminal output:
mkdir -p ./output
make -C ./riscv-tests/benchmarks median
make[1]: Entering directory
'/home/anshujit/work/ethernet-v0.5/vsim/riscv-tests/benchmarks'
cc median.o -o median
/usr/bin/ld: cannot open output file median: Is a directory
collect2: error: ld returned 1 exit status
<builtin>: recipe for target 'median' failed
make[1]: *** [median] Error 1
make[1]: Leaving directory
'/home/anshujit/work/ethernet-v0.5/vsim/riscv-tests/benchmarks'
Makefile:269: recipe for target 'output/median.riscv' failed
make: *** [output/median.riscv] Error 2
On Tue, Mar 13, 2018 at 3:47 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk>
wrote:
> Dear Anshujit,
>
> This is a very old release and a number of improvements and bug fixes have
> been made since then. You may find it profitable to compile the benchmark
> under Linux in the latest release , this will give a more helpful error
> message.
>
> Regards,
>
> Jonathan
>
>
>
> On 13/03/18 09:28, Anshujit Sharma wrote:
>
>> Dear all,
>>
>> I wanted to simulate lowRISC untether-v0.2 using verilator as described in
>> http://www.lowrisc.org/docs/untether-v0.2/vsim/
>>
>> System Config:
>> Ubuntu 16.04
>> Intel i5
>> Verilator V3.920
>>
>> Following is the sequence of commands used:
>> $cd lowrisc-chip
>> $source set_riscv_env.sh
>> $cd vsim
>> $export VERILATOR_ROOT=/path/to/verilator/root/directory
>> $make sim
>>
>> $make run-asm-tests
>> runs successfully
>>
>> $make run-bmarks-test
>> fails with the following terminal output:
>>
>> ./DefaultConfig-sim +max-cycles=100000000 +load=output/towers.riscv.hex |
>> /home/anshujit/work/lowrisc-chip/riscv/bin/spike-dasm >
>> output/towers.riscv.verilator.out && [ $PIPESTATUS -eq 0 ]
>> Core 0 get unsolved tohost code 21680
>> Makefile:201: recipe for target 'output/towers.riscv.verilator.out'
>> failed
>> make: *** [output/towers.riscv.verilator.out] Error 1
>>
>> Kindly, let me know how to debug this problem.
>>
>>
>>
9:08 p.m.
As Wei says, there is a problem in this Makefile, it has not been
maintained. But in any case these programs would need
to be modified to run bare-metal. You can find templates for bare-metal
programs in fpga/bare_metal/examples/boot.c
for example. Normal user programs will run in an operating system, which
is why we recommend running in Linux, for
which we give full instructions to install and run.
On 13/03/18 12:00, Wei Song wrote:
The benchmark tests from the original Rocket-Chip rely on the
host-interface (debugger in latest versions) for IO stream and file
support.
lowRISC SoC is untethered; therefore, there is no direct support for
these functions in the bare-metal mode.
It is actually supposed to fail due to these reasons.
As for the ethernet-v0.5 branch, the error seems like the Makefile
does not match with the directory.
However, as I said in the previous paragraph, 'make run-bmark-tests'
does not work out of the box even the Make file is fixed.
-Wei
On 13/03/18 19:16, Anshujit Sharma wrote:
> Thank you Sir for your reply.
>
> I moved to the ethernet-v0.5 branch and rebuilt the riscv-tools. Here
> again
> I faced some issues with run-bmark-tests.
> Following is the sequence of commands used:
> $cd ethernet-v0.5
> $source set_riscv_env.sh
> $cd vsim
> $export VERILATOR_ROOT=/path/to/verilator/root/directory
> $make sim
>
> $make run-asm-tests
> runs successfully
>
> $make run-bmarks-test
> fails with the following terminal output:
>
> mkdir -p ./output
> make -C ./riscv-tests/benchmarks median
> make[1]: Entering directory
> '/home/anshujit/work/ethernet-v0.5/vsim/riscv-tests/benchmarks'
> cc median.o -o median
> /usr/bin/ld: cannot open output file median: Is a directory
> collect2: error: ld returned 1 exit status
> <builtin>: recipe for target 'median' failed
> make[1]: *** [median] Error 1
> make[1]: Leaving directory
> '/home/anshujit/work/ethernet-v0.5/vsim/riscv-tests/benchmarks'
> Makefile:269: recipe for target 'output/median.riscv' failed
> make: *** [output/median.riscv] Error 2
>
>
>
> On Tue, Mar 13, 2018 at 3:47 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk>
> wrote:
>
>> Dear Anshujit,
>>
>> This is a very old release and a number of improvements and bug
>> fixes have
>> been made since then. You may find it profitable to compile the
>> benchmark
>> under Linux in the latest release , this will give a more helpful error
>> message.
>>
>> Regards,
>>
>> Jonathan
>>
>>
>>
>> On 13/03/18 09:28, Anshujit Sharma wrote:
>>
>>> Dear all,
>>>
>>> I wanted to simulate lowRISC untether-v0.2 using verilator as
>>> described in
>>> http://www.lowrisc.org/docs/untether-v0.2/vsim/
>>>
>>> System Config:
>>> Ubuntu 16.04
>>> Intel i5
>>> Verilator V3.920
>>>
>>> Following is the sequence of commands used:
>>> $cd lowrisc-chip
>>> $source set_riscv_env.sh
>>> $cd vsim
>>> $export VERILATOR_ROOT=/path/to/verilator/root/directory
>>> $make sim
>>>
>>> $make run-asm-tests
>>> runs successfully
>>>
>>> $make run-bmarks-test
>>> fails with the following terminal output:
>>>
>>> ./DefaultConfig-sim +max-cycles=100000000
>>> +load=output/towers.riscv.hex |
>>> /home/anshujit/work/lowrisc-chip/riscv/bin/spike-dasm >
>>> output/towers.riscv.verilator.out && [ $PIPESTATUS -eq 0 ]
>>> Core 0 get unsolved tohost code 21680
>>> Makefile:201: recipe for target 'output/towers.riscv.verilator.out'
>>> failed
>>> make: *** [output/towers.riscv.verilator.out] Error 1
>>>
>>> Kindly, let me know how to debug this problem.
>>>
>>>
>>>
>
2020
days inactive
2020
days old
4 comments
3 participants
participants (3)
-
Anshujit Sharma -
Dr Jonathan Kimmitt -
Wei Song