On 13 Jul 2018, at 06:52, Claire M. M. Wong <wmingming7(a)gmail.com&gt; wrote: What about the bus width for the nasti connected to the memory controller. In v0.5 release (NexyDDR) the bus is connected to DDR2 and the setting used are: set mem_data_width {64} set io_data_width {32} set axi_id_width {8} where as for release v0.2 (KC705) , DDR3 is used where the setting would be: set mem_data_width {128} set axi_id_width {9} it is compulsory to make the changes to accommodate DDR3 usage? also for release v0.2 SPI wrapper is used but that can be replaced with the SPI IP such as in v0.2 for the usage of SD-card right? > On Thu, Jul 12, 2018 at 10:40 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk&gt; wrote: > I do not see why you would need to use any software drivers from previous releases for that set up. Some drivers might > > not have changed however. Needless to say you have to use the correct version of gcc that comes with that release. > > It does not work if you set $RISCV to an old gcc install (this is to do with control and status register numbers primarily). > > If it still doesn't work it might be to do with clock management. Verilog timing simulation should show you if this is the case. > >> On 12/07/18 15:31, Claire M. M. Wong wrote: >> Thanks for the heads-up. >> >> As for Jonathan queations: >> >> Yes I started the porting by copying the v0.5 nexys4ddr directory to kc705. >> >> I commented the ethernet part in release v0.5. I want to minimise the scope of troubleshooting. I will deal with this part later on. >> >> As for the drivers, yes I did mix and modify a little from other releases. But not for the memory maps. >> >> Yes the NexyDDR only peripheral has been removed, that also includes the ADD_HID >> I have run the fpga simulation. I directly try out the make hello and it didnt work. As in I didnt get the Hello Work printout on the terminal. >> >> Just to be sure, is the drivers are strictly specific for each release? >> >> >> >>> On Thu, Jul 12, 2018 at 7:58 PM, Robert Mullins <Robert.Mullins(a)cl.cam.ac.uk&gt; wrote: >>> Hi Claire, >>> >>> Nice to hear you are experimenting with lowRISC. I hope Jonathan is >>> able to help. >>> >>> The lowrisc-dev mailing list might be best for this sort of discussion: >>> https://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/lowrisc-dev-li... >>> >>> Let us know how we can help by providing a few more details. >>> >>> v. best, >>> - Rob. >>> >>> >>> On 12 July 2018 at 12:48, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk&gt; wrote: >>> > Dear Claire, >>> > >>> > From your description it is impossible to know what is wrong with your >>> > 'several changes'. >>> > >>> > The main memory space by necessity will be larger on KC705. Other than that >>> > the memory map will be specific to the release and not to the board. >>> > >>> > The only files which should definitely be taken for the KC705 from previous >>> > releases are the Xilinx pinout and the dynamic memory config. >>> > >>> > Did you begin your port by copying the v0.5 nexys4ddr directory to kc705? >>> > >>> > Did you adapt the Ethernet module design to use MII instead of RMII ? >>> > >>> > Did you avoid mixing drivers, memory maps or RISCV files from different >>> > releases to prevent incompatible API changes from being propagated ? >>> > >>> > Did you remove the peripherals that are Nexys4DDR only (everything except >>> > serial, Ethernet, and SD-Card) >>> > >>> > Did you simulate the reworked parts of the design in Verilog ? >>> > >>> > If you are still stuck you need to provide more details of the changes you >>> > tried to make. >>> > >>> > Regards, >>> > Jonathan >>> > >>> > >>> > On 12/07/18 01:41, Claire M. M. Wong wrote: >>> > >>> > Hi all, >>> > >>> > I noticed there is a significant change in memory space mapping between >>> > lowriscv project v0.2 (developed for KC705) and project v0.3 onwards >>> > (developed for NexyDDR). Is the memory mapping has to be done in such way >>> > subject to the hardware board? >>> > >>> > In other words, suppose that I am trying to port project v0.5 to KC705, >>> > should I also change the memory space allocated for the IO and Mem? >>> > >>> > What about the drivers for the baremetal examples? are they subjected to the >>> > project's version and independent of the board? again if I would like to run >>> > the bare metal example Hello World for v0.5 implemented on KC705, should I >>> > be using the drivers that come with v0.5 or I have to use the ones provided >>> > in v0.2? >>> > >>> > Sorry if I sound very silly as I am still trying to figure out how to get >>> > things work with lowriscv project :) >>> > My main aim is to implement v0.5 on KC705. After several changes have been >>> > done, the work is still not successful. Therefore, I am trying to >>> > troubleshoot as much as I could to figure out what I might have missed. >>> > >>> > And I really need your advice and opinions. They will be very much >>> > appreciated :D >>> > >>> > Regards >>> > Claire >>> > -- >>> > You received this message because you are subscribed to the Google Groups >>> > "RISC-V HW Dev" group. >>> > To unsubscribe from this group and stop receiving emails from it, send an >>> > email to hw-dev+unsubscribe(a)groups.riscv.org. >>> > To post to this group, send email to hw-dev(a)groups.riscv.org. >>> > Visit this group at >>> > https://groups.google.com/a/groups.riscv.org/group/hw-dev/. >>> > To view this discussion on the web visit >>> > https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/84928d28-7c9e.... >>> > >>> > >>> > -- >>> > You received this message because you are subscribed to the Google Groups >>> > "RISC-V HW Dev" group. >>> > To unsubscribe from this group and stop receiving emails from it, send an >>> > email to hw-dev+unsubscribe(a)groups.riscv.org. >>> > To post to this group, send email to hw-dev(a)groups.riscv.org. >>> > Visit this group at >>> > https://groups.google.com/a/groups.riscv.org/group/hw-dev/. >>> > To view this discussion on the web visit >>> > https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/d57bca23-dd81.... >> >> >> >> -- >> Regards, >> Ming > -- Regards, Ming

Hi Jonathan, Thanks for the advice, that gives me a clearer direction now. What about the ADD_BRAM? In release v0.2 the nasti width is 128 bit while the release v0.5 uses 32 bits. Will that affect copying the boot code (boot.mem) to the bram? On Fri, Jul 13, 2018 at 2:18 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk <mailto:jrrk2@cam.ac.uk>> wrote: Dear Claire,   In v0.2 the DDR3 interface is 128 bits, but this is a performance optimisation, for your purposes it would be better to keep the width the same at 64 bits for both options, likewise the ID width. You can control this in the MIG config file. You also ideally should change the memory size in the Chisel config. Likewise the SD-Card IP is usable on KC705 but the card has an extra sd_reset pin, not being of the compact variant. As mentioned previously there are quite a few changes but it’s all a useful investigation and learning curve. Regards, Jonathan Sent from my iPhone On 13 Jul 2018, at 06:52, Claire M. M. Wong <wmingming7(a)gmail.com <mailto:wmingming7@gmail.com>> wrote: > What about the bus width for the nasti connected to the memory > controller. In v0.5 release (NexyDDR) the bus is connected to > DDR2 and the setting used are: > set mem_data_width {64} > set io_data_width {32} > set axi_id_width {8} > > where as for release v0.2 (KC705) , DDR3 is used where the > setting would be: > set mem_data_width {128} > set axi_id_width {9} > > it is compulsory to make the changes to accommodate DDR3 usage? > > also for release v0.2 SPI wrapper is used but that can be > replaced with the SPI IP such as in v0.2 for the usage of SD-card > right? > > > On Thu, Jul 12, 2018 at 10:40 PM, Dr Jonathan Kimmitt > <jrrk2(a)cam.ac.uk <mailto:jrrk2@cam.ac.uk>> wrote: > > I do not see why you would need to use any software drivers > from previous releases for that set up. Some drivers might > > not have changed however. Needless to say you have to use the > correct version of gcc that comes with that release. > > It does not work if you set $RISCV to an old gcc install > (this is to do with control and status register numbers > primarily). > > If it still doesn't work it might be to do with clock > management. Verilog timing simulation should show you if this > is the case. > > > On 12/07/18 15:31, Claire M. M. Wong wrote: >> Thanks for the heads-up. >> >> As for Jonathan queations: >> >> Yes I started the porting by copying the v0.5 nexys4ddr >> directory to kc705. >> >> I commented the ethernet part in release v0.5. I want to >> minimise the scope of troubleshooting. I will deal with this >> part later on. >> >> As for the drivers, yes I did mix and modify a little from >> other releases. But not for the memory maps. >> >> Yes the NexyDDR only peripheral has been removed, that also >> includes the ADD_HID >> >> I have run the fpga simulation. I directly try out the make >> hello and it didnt work. As in I didnt get the Hello Work >> printout on the terminal. >> >> Just to be sure, is the drivers are strictly specific for >> each release? >> >> >> >> On Thu, Jul 12, 2018 at 7:58 PM, Robert Mullins >> <Robert.Mullins(a)cl.cam.ac.uk >> <mailto:Robert.Mullins@cl.cam.ac.uk>> wrote: >> >> Hi Claire, >> >> Nice to hear you are experimenting with lowRISC. I hope >> Jonathan is >> able to help. >> >> The lowrisc-dev mailing list might be best for this sort >> of discussion: >> https://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/lowrisc-dev-li... >> <https://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/lowrisc-dev-li... >> >> Let us know how we can help by providing a few more details. >> >> v. best, >> - Rob. >> >> >> On 12 July 2018 at 12:48, Dr Jonathan Kimmitt >> <jrrk2(a)cam.ac.uk <mailto:jrrk2@cam.ac.uk>> wrote: >> > Dear Claire, >> > >> > From your description it is impossible to know what is >> wrong with your >> > 'several changes'. >> > >> > The main memory space by necessity will be larger on >> KC705. Other than that >> > the memory map will be specific to the release and not >> to the board. >> > >> > The only files which should definitely be taken for >> the KC705 from previous >> > releases are the Xilinx pinout and the dynamic memory >> config. >> > >> > Did you begin your port by copying the v0.5 nexys4ddr >> directory to kc705? >> > >> > Did you adapt the Ethernet module design to use MII >> instead of RMII ? >> > >> > Did you avoid mixing drivers, memory maps or RISCV >> files from different >> > releases to prevent incompatible API changes from >> being propagated ? >> > >> > Did you remove the peripherals that are Nexys4DDR only >> (everything except >> > serial, Ethernet, and SD-Card) >> > >> > Did you simulate the reworked parts of the design in >> Verilog ? >> > >> > If you are still stuck you need to provide more >> details of the changes you >> > tried to make. >> > >> > Regards, >> > Jonathan >> > >> > >> > On 12/07/18 01:41, Claire M. M. Wong wrote: >> > >> > Hi all, >> > >> > I noticed there is a significant change in memory >> space mapping between >> > lowriscv project v0.2 (developed for KC705) and >> project v0.3 onwards >> > (developed for NexyDDR). Is the memory mapping has to >> be done in such way >> > subject to the hardware board? >> > >> > In other words, suppose that I am trying to port >> project v0.5 to KC705, >> > should I also change the memory space allocated for >> the IO and Mem? >> > >> > What about the drivers for the baremetal examples? are >> they subjected to the >> > project's version and independent of the board? again >> if I would like to run >> > the bare metal example Hello World for v0.5 >> implemented on KC705, should I >> > be using the drivers that come with v0.5 or I have to >> use the ones provided >> > in v0.2? >> > >> > Sorry if I sound very silly as I am still trying to >> figure out how to get >> > things work with lowriscv project :) >> > My main aim is to implement v0.5 on KC705. After >> several changes have been >> > done, the work is still not successful. Therefore, I >> am trying to >> > troubleshoot as much as I could to figure out what I >> might have missed. >> > >> > And I really need your advice and opinions. They will >> be very much >> > appreciated :D >> > >> > Regards >> > Claire >> > -- >> > You received this message because you are subscribed >> to the Google Groups >> > "RISC-V HW Dev" group. >> > To unsubscribe from this group and stop receiving >> emails from it, send an >> > email to hw-dev+unsubscribe(a)groups.riscv.org >> <mailto:hw-dev%2Bunsubscribe@groups.riscv.org>. >> > To post to this group, send email to >> hw-dev(a)groups.riscv.org <mailto:hw-dev@groups.riscv.org>. >> > Visit this group at >> > >> https://groups.google.com/a/groups.riscv.org/group/hw-dev/ >> <https://groups.google.com/a/groups.riscv.org/group/hw-dev/>;. >> > To view this discussion on the web visit >> > >> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/84928d28-7c9e... >> <https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/84928d28-7c9e...;. >> > >> > >> > -- >> > You received this message because you are subscribed >> to the Google Groups >> > "RISC-V HW Dev" group. >> > To unsubscribe from this group and stop receiving >> emails from it, send an >> > email to hw-dev+unsubscribe(a)groups.riscv.org >> <mailto:hw-dev%2Bunsubscribe@groups.riscv.org>. >> > To post to this group, send email to >> hw-dev(a)groups.riscv.org <mailto:hw-dev@groups.riscv.org>. >> > Visit this group at >> > >> https://groups.google.com/a/groups.riscv.org/group/hw-dev/ >> <https://groups.google.com/a/groups.riscv.org/group/hw-dev/>;. >> > To view this discussion on the web visit >> > >> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/d57bca23-dd81... >> <https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/d57bca23-dd81...;. >> >> >> >> >> -- >> Regards, >> Ming > > > > > -- > Regards, > Ming -- Regards, Ming

Dear Jonathan, Right now I manage to get the basic release v0.5 works (without Ethernet and HDI and Flash)  on KC705 with simple printout Hello World on the terminal. However, I cant make the *hello.c* (compilation error) so instead, I modify the *int main()* from *boot.c* to just perform simple print string on the terminal. Also, I have to use the UART driver from release v0.3. Using the original UART driver from release v0.5 will only get the printout of the first character of the string. In other words, only "H" is printed on the terminal instead of "Hello World" Regards Claire On Fri, Jul 13, 2018 at 3:35 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk <mailto:jrrk2@cam.ac.uk>> wrote: Dear Claire, If you look at src/boot.mem you will see it is always 128-bits wide hex columns. The reduction to 32-bits happens on the CPU side and does not affect the initial readmemh() that happens during synthesis. But of course you must use the Verilog from the new version unless it is clear that the old version would be correct to carry forward. If you get things wrong there should be huge numbers of warning messages during Vivado synthesis, if you get it right there will be a handful of messages in very specific places (for example on the AXI clock converter). Of course you must not use any software tools from the old release. Regards, Jonathan On 13/07/18 08:28, Claire M. M. Wong wrote: > Hi Jonathan, > > Thanks for the advice, that gives me a clearer direction now. > > What about the ADD_BRAM? > > In release v0.2 the nasti width is 128 bit while the release v0.5 > uses 32 bits. Will that affect copying the boot code (boot.mem) > to the bram? > > > > On Fri, Jul 13, 2018 at 2:18 PM, Dr Jonathan Kimmitt > <jrrk2(a)cam.ac.uk <mailto:jrrk2@cam.ac.uk>> wrote: > > Dear Claire, >   In v0.2 the DDR3 interface is 128 bits, but this is a > performance optimisation, for your purposes it would be > better to keep the width the same at 64 bits for both > options, likewise the ID width. You can control this in the > MIG config file. You also ideally should change the memory > size in the Chisel config. Likewise the SD-Card IP is usable > on KC705 but the card has an extra sd_reset pin, not being of > the compact variant. As mentioned previously there are quite > a few changes but it’s all a useful investigation and > learning curve. > > Regards, > Jonathan > > Sent from my iPhone > > On 13 Jul 2018, at 06:52, Claire M. M. Wong > <wmingming7(a)gmail.com <mailto:wmingming7@gmail.com>> wrote: > >> What about the bus width for the nasti connected to the >> memory controller. In v0.5 release (NexyDDR) the bus is >> connected to DDR2 and the setting used are: >> set mem_data_width {64} >> set io_data_width {32} >> set axi_id_width {8} >> >> where as for release v0.2 (KC705) , DDR3 is used where the >> setting would be: >> set mem_data_width {128} >> set axi_id_width {9} >> >> it is compulsory to make the changes to accommodate DDR3 usage? >> >> also for release v0.2 SPI wrapper is used but that can be >> replaced with the SPI IP such as in v0.2 for the usage of >> SD-card right? >> >> >> On Thu, Jul 12, 2018 at 10:40 PM, Dr Jonathan Kimmitt >> <jrrk2(a)cam.ac.uk <mailto:jrrk2@cam.ac.uk>> wrote: >> >> I do not see why you would need to use any software >> drivers from previous releases for that set up. Some >> drivers might >> >> not have changed however. Needless to say you have to >> use the correct version of gcc that comes with that release. >> >> It does not work if you set $RISCV to an old gcc install >> (this is to do with control and status register numbers >> primarily). >> >> If it still doesn't work it might be to do with clock >> management. Verilog timing simulation should show you if >> this is the case. >> >> >> On 12/07/18 15:31, Claire M. M. Wong wrote: >>> Thanks for the heads-up. >>> >>> As for Jonathan queations: >>> >>> Yes I started the porting by copying the v0.5 nexys4ddr >>> directory to kc705. >>> >>> I commented the ethernet part in release v0.5. I want >>> to minimise the scope of troubleshooting. I will deal >>> with this part later on. >>> >>> As for the drivers, yes I did mix and modify a little >>> from other releases. But not for the memory maps. >>> >>> Yes the NexyDDR only peripheral has been removed, that >>> also includes the ADD_HID >>> >>> I have run the fpga simulation. I directly try out the >>> make hello and it didnt work. As in I didnt get the >>> Hello Work printout on the terminal. >>> >>> Just to be sure, is the drivers are strictly specific >>> for each release? >>> >>> >>> >>> On Thu, Jul 12, 2018 at 7:58 PM, Robert Mullins >>> <Robert.Mullins(a)cl.cam.ac.uk >>> <mailto:Robert.Mullins@cl.cam.ac.uk>> wrote: >>> >>> Hi Claire, >>> >>> Nice to hear you are experimenting with lowRISC. I >>> hope Jonathan is >>> able to help. >>> >>> The lowrisc-dev mailing list might be best for this >>> sort of discussion: >>> https://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/lowrisc-dev-li... >>> <https://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/lowrisc-dev-li... >>> >>> Let us know how we can help by providing a few more >>> details. >>> >>> v. best, >>> - Rob. >>> >>> >>> On 12 July 2018 at 12:48, Dr Jonathan Kimmitt >>> <jrrk2(a)cam.ac.uk <mailto:jrrk2@cam.ac.uk>> wrote: >>> > Dear Claire, >>> > >>> > From your description it is impossible to know >>> what is wrong with your >>> > 'several changes'. >>> > >>> > The main memory space by necessity will be larger >>> on KC705. Other than that >>> > the memory map will be specific to the release >>> and not to the board. >>> > >>> > The only files which should definitely be taken >>> for the KC705 from previous >>> > releases are the Xilinx pinout and the dynamic >>> memory config. >>> > >>> > Did you begin your port by copying the v0.5 >>> nexys4ddr directory to kc705? >>> > >>> > Did you adapt the Ethernet module design to use >>> MII instead of RMII ? >>> > >>> > Did you avoid mixing drivers, memory maps or >>> RISCV files from different >>> > releases to prevent incompatible API changes from >>> being propagated ? >>> > >>> > Did you remove the peripherals that are Nexys4DDR >>> only (everything except >>> > serial, Ethernet, and SD-Card) >>> > >>> > Did you simulate the reworked parts of the design >>> in Verilog ? >>> > >>> > If you are still stuck you need to provide more >>> details of the changes you >>> > tried to make. >>> > >>> > Regards, >>> > Jonathan >>> > >>> > >>> > On 12/07/18 01:41, Claire M. M. Wong wrote: >>> > >>> > Hi all, >>> > >>> > I noticed there is a significant change in memory >>> space mapping between >>> > lowriscv project v0.2 (developed for KC705) and >>> project v0.3 onwards >>> > (developed for NexyDDR). Is the memory mapping >>> has to be done in such way >>> > subject to the hardware board? >>> > >>> > In other words, suppose that I am trying to port >>> project v0.5 to KC705, >>> > should I also change the memory space allocated >>> for the IO and Mem? >>> > >>> > What about the drivers for the baremetal >>> examples? are they subjected to the >>> > project's version and independent of the board? >>> again if I would like to run >>> > the bare metal example Hello World for v0.5 >>> implemented on KC705, should I >>> > be using the drivers that come with v0.5 or I >>> have to use the ones provided >>> > in v0.2? >>> > >>> > Sorry if I sound very silly as I am still trying >>> to figure out how to get >>> > things work with lowriscv project :) >>> > My main aim is to implement v0.5 on KC705. After >>> several changes have been >>> > done, the work is still not successful. >>> Therefore, I am trying to >>> > troubleshoot as much as I could to figure out >>> what I might have missed. >>> > >>> > And I really need your advice and opinions. They >>> will be very much >>> > appreciated :D >>> > >>> > Regards >>> > Claire >>> > -- >>> > You received this message because you are >>> subscribed to the Google Groups >>> > "RISC-V HW Dev" group. >>> > To unsubscribe from this group and stop receiving >>> emails from it, send an >>> > email to hw-dev+unsubscribe(a)groups.riscv.org >>> <mailto:hw-dev%2Bunsubscribe@groups.riscv.org>. >>> > To post to this group, send email to >>> hw-dev(a)groups.riscv.org >>> <mailto:hw-dev@groups.riscv.org>. >>> > Visit this group at >>> > >>> https://groups.google.com/a/groups.riscv.org/group/hw-dev/ >>> <https://groups.google.com/a/groups.riscv.org/group/hw-dev/>;. >>> > To view this discussion on the web visit >>> > >>> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/84928d28-7c9e... >>> <https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/84928d28-7c9e...;. >>> > >>> > >>> > -- >>> > You received this message because you are >>> subscribed to the Google Groups >>> > "RISC-V HW Dev" group. >>> > To unsubscribe from this group and stop receiving >>> emails from it, send an >>> > email to hw-dev+unsubscribe(a)groups.riscv.org >>> <mailto:hw-dev%2Bunsubscribe@groups.riscv.org>. >>> > To post to this group, send email to >>> hw-dev(a)groups.riscv.org >>> <mailto:hw-dev@groups.riscv.org>. >>> > Visit this group at >>> > >>> https://groups.google.com/a/groups.riscv.org/group/hw-dev/ >>> <https://groups.google.com/a/groups.riscv.org/group/hw-dev/>;. >>> > To view this discussion on the web visit >>> > >>> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/d57bca23-dd81... >>> <https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/d57bca23-dd81...;. >>> >>> >>> >>> >>> -- >>> Regards, >>> Ming >> >> >> >> >> -- >> Regards, >> Ming > > > > > -- > Regards, > Ming -- Regards, Ming

Dear Claire, It looks like your persistence is paying off and you are getting the hang of this porting activity. If you would like to clone our repository on github (if not already done) and push your changes this will make it a lot easier for me to reproduce any issues you are having. If we can tie down the discrepancies we can adopt your version as the official KC705 port for ethernet-v0.5, since I am not aware that anyone else is publicly working on that activity. Any operational contribution you make will be acknowledged in the documentation of the next release if it can be used going forward. Regards, Jonathan On 13/07/18 09:38, Claire M. M. Wong wrote: Dear Jonathan, Right now I manage to get the basic release v0.5 works (without Ethernet and HDI and Flash) on KC705 with simple printout Hello World on the terminal. However, I cant make the *hello.c* (compilation error) so instead, I modify the *int main()* from *boot.c* to just perform simple print string on the terminal. Also, I have to use the UART driver from release v0.3. Using the original UART driver from release v0.5 will only get the printout of the first character of the string. In other words, only "H" is printed on the terminal instead of "Hello World" Regards Claire On Fri, Jul 13, 2018 at 3:35 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk&gt; wrote: > Dear Claire, > > If you look at src/boot.mem you will see it is always 128-bits wide hex > columns. The reduction to 32-bits happens on the CPU side and does not > affect > > the initial readmemh() that happens during synthesis. But of course you > must use the Verilog from the new version unless it is clear that the old > version > > would be correct to carry forward. If you get things wrong there should > be huge numbers of warning messages during Vivado synthesis, if you get it > right > > there will be a handful of messages in very specific places (for example > on the AXI clock converter). > > Of course you must not use any software tools from the old release. > Regards, > Jonathan > > > On 13/07/18 08:28, Claire M. M. Wong wrote: > > Hi Jonathan, > > Thanks for the advice, that gives me a clearer direction now. > > What about the ADD_BRAM? > > In release v0.2 the nasti width is 128 bit while the release v0.5 uses 32 > bits. Will that affect copying the boot code (boot.mem) to the bram? > > > > On Fri, Jul 13, 2018 at 2:18 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk&gt; > wrote: > >> Dear Claire, >> In v0.2 the DDR3 interface is 128 bits, but this is a performance >> optimisation, for your purposes it would be better to keep the width the >> same at 64 bits for both options, likewise the ID width. You can control >> this in the MIG config file. You also ideally should change the memory size >> in the Chisel config. Likewise the SD-Card IP is usable on KC705 but the >> card has an extra sd_reset pin, not being of the compact variant. As >> mentioned previously there are quite a few changes but it’s all a useful >> investigation and learning curve. >> >> Regards, >> Jonathan >> >> Sent from my iPhone >> >> On 13 Jul 2018, at 06:52, Claire M. M. Wong <wmingming7(a)gmail.com&gt; >> wrote: >> >> What about the bus width for the nasti connected to the memory >> controller. In v0.5 release (NexyDDR) the bus is connected to DDR2 and the >> setting used are: >> set mem_data_width {64} >> set io_data_width {32} >> set axi_id_width {8} >> >> where as for release v0.2 (KC705) , DDR3 is used where the setting would >> be: >> set mem_data_width {128} >> set axi_id_width {9} >> >> it is compulsory to make the changes to accommodate DDR3 usage? >> >> also for release v0.2 SPI wrapper is used but that can be replaced with >> the SPI IP such as in v0.2 for the usage of SD-card right? >> >> >> On Thu, Jul 12, 2018 at 10:40 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk&gt; >> wrote: >> >>> I do not see why you would need to use any software drivers from >>> previous releases for that set up. Some drivers might >>> >>> not have changed however. Needless to say you have to use the correct >>> version of gcc that comes with that release. >>> >>> It does not work if you set $RISCV to an old gcc install (this is to do >>> with control and status register numbers primarily). >>> >>> If it still doesn't work it might be to do with clock management. >>> Verilog timing simulation should show you if this is the case. >>> >>> On 12/07/18 15:31, Claire M. M. Wong wrote: >>> >>> Thanks for the heads-up. >>> >>> As for Jonathan queations: >>> >>> Yes I started the porting by copying the v0.5 nexys4ddr directory to >>> kc705. >>> >>> I commented the ethernet part in release v0.5. I want to minimise the >>> scope of troubleshooting. I will deal with this part later on. >>> >>> As for the drivers, yes I did mix and modify a little from other >>> releases. But not for the memory maps. >>> >>> Yes the NexyDDR only peripheral has been removed, that also includes >>> the ADD_HID >>> I have run the fpga simulation. I directly try out the make hello and >>> it didnt work. As in I didnt get the Hello Work printout on the terminal. >>> >>> Just to be sure, is the drivers are strictly specific for each release? >>> >>> >>> >>> On Thu, Jul 12, 2018 at 7:58 PM, Robert Mullins < >>> Robert.Mullins(a)cl.cam.ac.uk&gt; wrote: >>> >>>> Hi Claire, >>>> >>>> Nice to hear you are experimenting with lowRISC. I hope Jonathan is >>>> able to help. >>>> >>>> The lowrisc-dev mailing list might be best for this sort of discussion: >>>> https://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/l >>>> owrisc-dev-lists.lowrisc.org >>>> >>>> Let us know how we can help by providing a few more details. >>>> >>>> v. best, >>>> - Rob. >>>> >>>> >>>> On 12 July 2018 at 12:48, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk&gt; wrote: >>>> > Dear Claire, >>>> > >>>> > From your description it is impossible to know what is wrong with >>>> your >>>> > 'several changes'. >>>> > >>>> > The main memory space by necessity will be larger on KC705. Other >>>> than that >>>> > the memory map will be specific to the release and not to the board. >>>> > >>>> > The only files which should definitely be taken for the KC705 from >>>> previous >>>> > releases are the Xilinx pinout and the dynamic memory config. >>>> > >>>> > Did you begin your port by copying the v0.5 nexys4ddr directory to >>>> kc705? >>>> > >>>> > Did you adapt the Ethernet module design to use MII instead of RMII ? >>>> > >>>> > Did you avoid mixing drivers, memory maps or RISCV files from >>>> different >>>> > releases to prevent incompatible API changes from being propagated ? >>>> > >>>> > Did you remove the peripherals that are Nexys4DDR only (everything >>>> except >>>> > serial, Ethernet, and SD-Card) >>>> > >>>> > Did you simulate the reworked parts of the design in Verilog ? >>>> > >>>> > If you are still stuck you need to provide more details of the >>>> changes you >>>> > tried to make. >>>> > >>>> > Regards, >>>> > Jonathan >>>> > >>>> > >>>> > On 12/07/18 01:41, Claire M. M. Wong wrote: >>>> > >>>> > Hi all, >>>> > >>>> > I noticed there is a significant change in memory space mapping >>>> between >>>> > lowriscv project v0.2 (developed for KC705) and project v0.3 onwards >>>> > (developed for NexyDDR). Is the memory mapping has to be done in >>>> such way >>>> > subject to the hardware board? >>>> > >>>> > In other words, suppose that I am trying to port project v0.5 to >>>> KC705, >>>> > should I also change the memory space allocated for the IO and Mem? >>>> > >>>> > What about the drivers for the baremetal examples? are they >>>> subjected to the >>>> > project's version and independent of the board? again if I would >>>> like to run >>>> > the bare metal example Hello World for v0.5 implemented on KC705, >>>> should I >>>> > be using the drivers that come with v0.5 or I have to use the ones >>>> provided >>>> > in v0.2? >>>> > >>>> > Sorry if I sound very silly as I am still trying to figure out how >>>> to get >>>> > things work with lowriscv project :) >>>> > My main aim is to implement v0.5 on KC705. After several changes >>>> have been >>>> > done, the work is still not successful. Therefore, I am trying to >>>> > troubleshoot as much as I could to figure out what I might have >>>> missed. >>>> > >>>> > And I really need your advice and opinions. They will be very much >>>> > appreciated :D >>>> > >>>> > Regards >>>> > Claire >>>> > -- >>>> > You received this message because you are subscribed to the Google >>>> Groups >>>> > "RISC-V HW Dev" group. >>>> > To unsubscribe from this group and stop receiving emails from it, >>>> send an >>>> > email to hw-dev+unsubscribe(a)groups.riscv.org. >>>> > To post to this group, send email to hw-dev(a)groups.riscv.org. >>>> > Visit this group at >>>> > https://groups.google.com/a/groups.riscv.org/group/hw-dev/. >>>> > To view this discussion on the web visit >>>> > https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/ >>>> 84928d28-7c9e-4eb4-9df0-00cf67e5a8e2%40groups.riscv.org. >>>> > >>>> > >>>> > -- >>>> > You received this message because you are subscribed to the Google >>>> Groups >>>> > "RISC-V HW Dev" group. >>>> > To unsubscribe from this group and stop receiving emails from it, >>>> send an >>>> > email to hw-dev+unsubscribe(a)groups.riscv.org. >>>> > To post to this group, send email to hw-dev(a)groups.riscv.org. >>>> > Visit this group at >>>> > https://groups.google.com/a/groups.riscv.org/group/hw-dev/. >>>> > To view this discussion on the web visit >>>> > https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/ >>>> d57bca23-dd81-9278-bb42-b31625c2af75%40cam.ac.uk. >>>> >>> >>> >>> >>> -- >>> Regards, >>> Ming >>> >>> >>> >> >> >> -- >> Regards, >> Ming >> >> > > > -- > Regards, > Ming > > > -- Regards, Ming