Here is an update on my work on untethering a lowRISC SoC.
The hardware part of the initial untethered lowRISC chip is nearly finished.
A Xilinx KC705 board is used to develop the untethered SoC but low-end
development boards are scheduled to be supported once the initial code
release is ready.
Summary of current changes:
Memory mapped IO has been added using a separated uncached Tilelink.
The original Rocket HTIF has been removed.
Tilelink to NASTI/NASTI-Lite bridges are implemented.
All chisel components (Rocket cores, L2 caches) are encapsulated in
a Chisel island with only two NASTI interface exposed.
A NASTI on-chip interconnect (crossbar, buffer, Lite/NASTI bridge)
is provided using SystemVerilog.
UART (Xilinx IP) connected and tested.
SD (Xilinx SPI IP) connected and tested. Software support for FatFS
DDR3 RAM and Memory controller (XIlinx IP) is connected and tested.
Bare-metal bootloader: boot from on-chip BRAM, copy a hello
executable from SD to DDR3 RAM and then reset to DDR3 running the hello
Get rid of the VCS simulation environment and replaced it with
Full Makefile support for FPGA project and FPGA simulation.
Modify the RISC-V Linux and port it to the untethered lowRISC SoC.
Currently thinking of revising the Berkeley Bootloader to avoid directly
porting a Linux Kernel.