Here is an update from the lowRISC project.
Over the past several months, we’ve been working to provide a standalone
or ‘untethered’ SoC. Cores in the original Rocket chip rely on
communicating with a companion processor via the host-target interface
(HTIF) to access peripherals and I/O. This release removes this
requirement, adding an I/O bus and instantiating FPGA peripherals. The
accompanying tutorial, written by Wei Song, describes how to build this
code release and explains the underlying structural changes. We support
both the Xilinx KC705 and the lower-priced Nexys4 DDR development
boards. We would gladly welcome assistance in supporting other boards.
Please note that the codebase temporarily lacks support for tagged
memory included in the previous release. We plan to re-integrate tagged
memory support with additional optimisations early next year. You can
find a detailed list of changes in the release notes. One highlight is
support for RTL simulation using the open-source Verilator tool.
We hope to see many of you at the 3rd RISC-V Workshop in January, where
Wei Song and Alex Bradbury will be presenting about lowRISC.
The release tutorial: http://www.lowrisc.org/docs/untether-v0.2/
Release note: http://www.lowrisc.org/docs/untether-v0.2/release/
Code release repo: https://github.com/lowRISC/lowrisc-chip/