Dear Kritik, A usable debug capability is a high priority. The implementation of the RISCV debug specification on Rocket will need some adaptation since TAP IR lengths and available user codes on Xilinx are restricted, also the wiring of the JTAG signals on the simulation platform needs adapting to real hardware. We have not thought it worthwhile to generate any release notes for the new Rocket since a key part, the Linux port, is not yet working. It will take considerable effort to get the tag cache working again, but a student of Stefan is working on adapting the trace debugger as I understand it. Regards, Jonathan Sent from my iPhone > On 26 Dec 2017, at 06:24, kritik bhimani <bhimanikritik(a)gmail.com&gt; wrote: > > Hi Alex/Stefan, I saw that you both are a part of the debug taskgroup. So > could you please let me know regarding any activity on Trace feature. I > wanted to know which features of the debug in previous revisions of lowRISC > should be ported to work with the latest rocket-chip. As features like MAM > and System Control Module I don't think are needed any more. Instead I > think the aim should rather be to extend the existing debug infrastructure > in the latest rocket-chip to use features from open soc debug like glip, > CTM and STM and at the same time be compliant with the debug spec. This > will also help in future to integrate latest rocket-chip into lowRISC. > Secondly can an issue on the GitHub repo be raised stating all the features > that are yet to be ported from the previous revisions like trace debug, tag > cache and related infrastructure.

On 26 December 2017 at 06:24, kritik bhimani <bhimanikritik(a)gmail.com&gt; wrote: > Hi Alex/Stefan, I saw that you both are a part of the debug taskgroup. So > could you please let me know regarding any activity on Trace feature. I > wanted to know which features of the debug in previous revisions of lowRISC > should be ported to work with the latest rocket-chip. As features like MAM > and System Control Module I don't think are needed any more. Instead I think > the aim should rather be to extend the existing debug infrastructure in the > latest rocket-chip to use features from open soc debug like glip, CTM and > STM and at the same time be compliant with the debug spec. The debug working group are focusing on finalising the run-control spec currently so there is no real activity on trace. Sadly the terms of RISC-V Foundation membership make it impossible to share non-public information about taskgroup discussions. > This will also > help in future to integrate latest rocket-chip into lowRISC. Secondly can an > issue on the GitHub repo be raised stating all the features that are yet to > be ported from the previous revisions like trace debug, tag cache and > related infrastructure. That's definitely a good idea. As you may have seen from discussion on the list, Jonathan has recently integrated Ethernet support using open source IP but this is based on the previous rocket-chip release. Once the Cambridge team is back in the office in the new year, we'll aim to enumerate the remaining required work for a lowRISC platform release using a newer rocket-chip, and as you suggest - outline the tasks needed to further extend that. Best, Alex

On 27 Dec 2017, at 07:28, Luke Kenneth Casson Leighton <lkcl(a)lkcl.net&gt; wrote: if it is easy to adapt, i am aware of two pre-existing debugging front-ends, one is dan glisselquest's ZipCPU UART debug system, and the other is sergey's ethernet (UDP-based) debugging system. both have libre tools available and are fully documented. sergey's implementation actually has the advantage that it's already linked in to a RISC-V core. https://github.com/sergeykhbr/riscv_vhdl professor kimmit am i right in thinking that the ethernet-v0.5 branch actually incorporated the *full* capabilities of sergey's ethernet core, *including* the debug-over-UDP-ethernet capability? correct me if i'm wrong, i seem to recall last week mention that this was the reason why the lowrisc team was actively considering *dropping* sergey's ethernet hard macro. i did wonder about that, why not simply make a #define ... oh it's *already* been added: https://github.com/sergeykhbr/riscv_vhdl/blob/master/rocket_soc/work/conf... so it's possible to disable/enable the ethernet debugging, already. also i just noticed his last commit https://github.com/sergeykhbr/riscv_vhdl/commit/cb0d1d9a675709d993de99153... [+] Add VHDL uart debug port (TAP) to SoC top level. Full verification not finished yet. so i believe that would be a _third_ method by which low-level debugging could be achieved. sergey's approach has the advantage that he appears to be also providing libre debug GUI front-end tool source code as well. hth, l.