On 12 August 2016 at 16:59, Brad Walker <bwalker(a)musings.com&gt; wrote: > I've evaluating if there is an implementation of lowrisc for an FPGA. > > Are there any implementations for the Zynq processors currently? Hi Brad, please see our code releases along with associated documentation at http://www.lowrisc.org/docs/ As of the untethered release, we no longer support Zynq platforms such as the Zedboard, although an interested community member could add it back (I believe with appropriate fiddling it's possible to access the SD card pins from the programmable logic side). The Nexys4 DDR is our recommended starter board http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recom...

On 12/08/2016 18:29, Manuel A. Fernandez Montecelo wrote: > > Is that the same as for the SiFive RISC-V 64? > > BTW, does lowRISC implement the Userland 2.1 spec (and Supervisor 1.7, I > suppose), or still at 2.0? > lowRISC uses the UC Berkeley's Rocket-chip implementation up to May 2016 with extra features including a trace debugger, standalone (untethered) SoC, SD support in Linux, XIP flash, etc. The RISC-V user spec 2.1 was out in May. The lowRISC's version of Rocket core should be at least 2.0. As for the privileged spec, lowRISC uses the priv-1.9 branch from ucb-bar; therefore, it should be at least more advanced than 1.7.