Last week, I got ccall and csetoffest CHERI instructions added to
RISC-V binutils, as the first two instructions with their expected
arguments, tested with as, objdump and ld. Then I added support to
spike to recognize the CHERI extension and enable it on run-time
(spike --extension=cheri) same as dummy_rocc (rocket custom
co-processor). Now that spike has its own CHERI co-processor base, it
can recognize CHERI instructions (tested with ccall and csetoffset).
This week I am going to thoroughly read the CHERI manual (CL-TR-981)
again to implement the expected behavior of the two instructions.
After this, I will continue adding more instructions, which will be
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last week I haven't had much time and didn't accomplish much but I did manage
to get pv6 booting in superuser mode and with Sv48 page tables. It was mostly
fighting the assembler and the link script ;) only to find out pretty late that
64 bit CPUs are not supposed to have Sv32 page tables O:-)
I decided to go the raw way without bbl for now to make things easier to
develop and flourish but that also means its now stranding on console I/O and I
have to consider what kind of devices to support and in what way. Good way to
investigate and work out the ideas I have described in my proposal. For this
I'll have to add the CSRs for device selection and to create an emulating
backend if even for a console and disk. Downside is of course that others
can't test it without a patched spike.
Anyway, I'll keep you informed.