10:13 a.m.
On 5 Sep 2016 08:22, "Hesham Almatary" <heshamelmatary(a)gmail.com> wrote:
This week I am going to thoroughly read the CHERI manual (CL-TR-981)
again to implement the expected behavior of the two instructions.
After this, I will continue adding more instructions, which will be
relatively easier.
Thanks for kicking off the thread this week Hesham, sounds like interesting
stuff.
Last week our interns at the lab finished up their work, so I've spent
some time proof reading their write up. We hope to get that posted soon.
The Computer Lab also played host to an OpenBSD hackathon which led to some
interesting discussions regarding defenses against code reuse attacks like
ROP. The addition of support for execute-only pages in 1.9 of the
privileged spec will be good to explore.
I'm running the LLVM Cauldron in Hebden Bridge on Thursday so it may not be
a particularly productive week otherwise. I will continue to work on risc-v
llvm codegen.
Alex
10:18 a.m.
New subject: What are you working on this week?
Hi all,
I spent the last days with updating my other project (OpTiMSoC) with the
updated debug infrastructure, so that it now shares the same debugging
with lowRISC. As a result there were some structural changes to Open SoC
Debug that I still have to merge to lowRISC.
Beside that it is mainly planning for the next steps. The main things are:
- Run-control support for the "simple spec" which Pulpino uses
- A separate debug clock domain
- UART XON/XOFF flow control for boards without RTS/CTS
- Preparing for a second (high speed) physical interface
We have some helping hands for parts of this. As I will be on parental
leave for a month after this week, I won't finish it all before ORCONF,
which you all hopefully come to.
Cheers,
Stefan
5:32 p.m.
New subject: What are you working on this week?
As predicted, last week wasn't massively productive. The LLVM Cauldron
was very successful though, and videos from the event are already
edited and uploaded (thanks to Simon Cook from Embecosm)
http://llvm.org/devmtg/2016-09/#schedule
https://www.youtube.com/playlist?list=PLOGTP9W1DX5X9dNzT02d-CP-OWOR4kKpq
I'll be attending the ARM Research Summit
<https://developer.arm.com/research/summit/> on Thursday and Friday
this week and am off today on annual leave, so it's going to be a very
compressed week. One thing I'd definitely like to get sorted is the
remaining questions about parametrising the RISC-V instruction set by
the RegisterClass (e.g. 32-bit, 64-bit, or even 128-bit GPRs) in the
LLVM backend.
What are you working on this week?
Alex
10:37 p.m.
New subject: What are you working on this week?
Hi folks,
in Dutch there is a saying `writing is scrapping' and this week i'm busy
rewriting my hardware hypervisor proposal. I've simplified it quite a lot for
ease of implementation.
Other than that, i might go on with my PV6 port. Would it be better if i base
the PV6 port / work on the current lowRISC spike sim? or on modifying the
standard spike sim?
Reinoud
7:14 a.m.
New subject: What are you working on this week?
Hi,
So last week, I added 26 (out of 40?) CHERI instructions to binutils
and spike. No checking for exceptions yet, just simulating the
expected behavior of instructions. Currently testing using an assembly
program. Would be good if there's already some assembly regression
test that I can use (or port), I'll have to check.
This week I am going to work on the remaining instructions, and if
there is enough time, I'll start accounting for CHERI exceptions for
each instruction and how to integrate them into RISC-V exceptions.
Best,
Hesham
On Tue, Sep 13, 2016 at 6:37 AM, Reinoud Zandijk <reinoud(a)netbsd.org> wrote:
Hi folks,
in Dutch there is a saying `writing is scrapping' and this week i'm busy
rewriting my hardware hypervisor proposal. I've simplified it quite a lot for
ease of implementation.
Other than that, i might go on with my PV6 port. Would it be better if i base
the PV6 port / work on the current lowRISC spike sim? or on modifying the
standard spike sim?
Reinoud
--
Hesham
9 a.m.
New subject: What are you working on this week?
On 12 September 2016 at 21:37, Reinoud Zandijk <reinoud(a)netbsd.org> wrote:
Other than that, i might go on with my PV6 port. Would it be better
if i base
the PV6 port / work on the current lowRISC spike sim? or on modifying the
standard spike sim?
You're best off basing your work on https://github.com/riscv/riscv-isa-sim
Alex
8:03 p.m.
New subject: What are you working on this week?
I think we missed last week - my excuse is I was busy feeling sorry
for myself with a cold.
This week my first priority is completing a draft of a grant
application I'm working on, that would help further fund lowRISC CIC's
activities. I've been taking a keen interest in the ongoing discussion
about adding support for 'tagged pointers' in the RISC-V isa-dev list
<https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/Pm9mso-urM8/nR...;.
I of course prefer to call this embedded metadata to reduce confusion
with lowRISC tagged memory location support. I feel the combination of
tagged memory and embedded metadata (plus potentially some extra
support for processing this data, perhaps through offloading to a
minion core) could be very powerful.
I'm working on my upcoming presentation at ORConf <http://orconf.org/>
in a couple of weeks time and hope to see many of you there.
On the LLVM side, I've been having some really useful discussions
upstream regarding avoiding duplicating all instruction definitions
for RV32, RV64 and potentially RV128 (the base instruction set has the
same encoding, but operates on registers of different sizes and so
LLVM codegen currently needs a separate definition). See the thread
regarding adding support for variable-sized register classes
<http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html>;.
If you're interested in LLVM in general, you may also be interested
that slides+videos from the LLVM Cauldron event I organised are now
online http://llvm.org/devmtg/2016-09/#schedule. Once the draft of the
grant application is out of the way, I should be spending the majority
of the rest of the week pushing forward RISC-V LLVM.
What are you up to this week?
Alex
9:40 p.m.
New subject: What are you working on this week?
hi folks,
What are you up to this week?
haven't had much time lately but I managed to get PV6 (the xv6 port to riscv)
to boot and display stuff on a console, but of course panics very early due to
unimplemented functions. This week I'll try to at least get the memory map
discovery up and running and we'll see what else I got time for. Maybe a first
hypervisor proof-of-concept device, who knows :)
Cheer,
Reinoud
10:32 p.m.
New subject: What are you working on this week?
Hello,
As a part of the plan to bring back tagged memory support in lowRISC, I
have recently started re-adding tagged memory support in the Spike ISA
simulator.
Currently I have added tags to all registers in the register file and
the program counter. This week I am working on the behvaioural model of
the tag cache.
Hopefully several weeks later we can have a simulation model to work with.
BTW, I have recently changed the Verilator compilation options to
support parallel make (make -j).
I hope this would significantly reduce the simulation compilation time
if you get a multi-core machine.
Best regards,
Wei
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8 comments
5 participants
participants (5)
-
Alex Bradbury -
Hesham Almatary -
Reinoud Zandijk -
Stefan Wallentowitz -
Wei Song