I think we missed last week - my excuse is I was busy feeling sorry
for myself with a cold.
This week my first priority is completing a draft of a grant
application I'm working on, that would help further fund lowRISC CIC's
activities. I've been taking a keen interest in the ongoing discussion
about adding support for 'tagged pointers' in the RISC-V isa-dev list
I of course prefer to call this embedded metadata to reduce confusion
with lowRISC tagged memory location support. I feel the combination of
tagged memory and embedded metadata (plus potentially some extra
support for processing this data, perhaps through offloading to a
minion core) could be very powerful.
I'm working on my upcoming presentation at ORConf <http://orconf.org/>
in a couple of weeks time and hope to see many of you there.
On the LLVM side, I've been having some really useful discussions
upstream regarding avoiding duplicating all instruction definitions
for RV32, RV64 and potentially RV128 (the base instruction set has the
same encoding, but operates on registers of different sizes and so
LLVM codegen currently needs a separate definition). See the thread
regarding adding support for variable-sized register classes
If you're interested in LLVM in general, you may also be interested
that slides+videos from the LLVM Cauldron event I organised are now
. Once the draft of the
grant application is out of the way, I should be spending the majority
of the rest of the week pushing forward RISC-V LLVM.
What are you up to this week?