I was able to successfully port the untethered design to a custom Virtex 7
I also ran the hello world example, which ran successfully.
When I try to run the dram test, the print stops after the 1st msg:
DRAM test program.
Write block @0 using key 0
I did a little debugging and added a print step inside the dram.c code,
line: 57, inside the for loop.
It gets stuck at step 8 (i.e i iterated 8 times.)
Virtex 7 2000T - xc7v2000tflg1925-1
lowrisc - untether v0.2
MIG UI Clock @ 100 MHz
Uart, BRAM, SPI-SD, Core - all running at 25 MHz
I have configured the axi_clock_convertor to 1:4 ratio for the above clock
Kindly let me know how to proceed debugging this issue further.
Thanks & Regards,