Re: [lowrisc-dev] BRAM logic in chip_top.sv
If you are talking about the boot memory block RAM controller, it is
written in such
a way as to allow different widths of AXI bus to be used, as well as to
make it convenient to
read in a program and update it via data2mem. As such part of the
objectives of the project
are to make it as library independent as possible and to use RAM
inference where possible.
This means minimizing structural inferences as much as possible. Having
said that there are
several authors plus adaptations of previously existing code involved as
well. I haven't used IP-XACT at all.
On 23/11/17 08:50, Olof Kindgren wrote:
One of the things I would like to do with LowRISC is a clean
separation of
structural and behavioural logic to eventually use IP-XACT or other
configuration formats to easier build modular designs
In chip_top.sv I found a big chunk of logic that seems to be related to
creating an boot memory.
Could someone please enlighten me what this code is supposed to do? I can't
really figure out from looking at the source, and the elaborated design
doesn't provide any addtional clues.
//Olof