4:52 p.m.
The hello world test uses only internal block ram. So not much to go wrong.
As soon as you exercise DDR memory, the processor will hang if the AXI
bus does
not respond. The situation is complicated by the presence of caching
which might mean
you don't see the problem straight away.
I suggest you run the DRAM example design that comes with MIG generator
(right click on the MIG IP in Vivado and use 'Open IP example design')
to prove that
your MIG settings are correct. This can be done in simulation and the
real FPGA.
If it passes the Vivado example design, it is a simple matter to capture
the settings in
mig_config.prj for lowrisc. Also pay attention to any interface signals
that might be different
in that version of the MIG IP.
There may also be a pre-configured MIG project for your board on the
manufacturer's website already
for comparison. Also check your board revision, sometimes the DDR chip
changes between revisions
and this could require MIG settings file to be changed.
On 31/01/18 12:41, Anup Kini wrote:
Hi All,
I was able to successfully port the untethered design to a custom Virtex 7
2000T device.
I also ran the hello world example, which ran successfully.
When I try to run the dram test, the print stops after the 1st msg:
DRAM test program.
Write block @0 using key 0
I did a little debugging and added a print step inside the dram.c code,
line: 57, inside the for loop.
It gets stuck at step 8 (i.e i iterated 8 times.)
SetUp details:
Vivado 2015.4
Virtex 7 2000T - xc7v2000tflg1925-1
lowrisc - untether v0.2
MIG UI Clock @ 100 MHz
Uart, BRAM, SPI-SD, Core - all running at 25 MHz
I have configured the axi_clock_convertor to 1:4 ratio for the above clock
setting.
Kindly let me know how to proceed debugging this issue further.
Thanks & Regards,
Anup Kini.