Problem loading Linux on LowRISC-v0.5 with trace debugger support
by Imran Wali
Hi,
I am trying to boot Linux on LowRISC-v0.5 with debugger support. I have used two approaches to do that:
1. To build the "jump" example with debugger support (CONFIG=Nexys4DebugConfig make jump) and program the FPGA. Then use the trace debugger interface to load Linux image to the DDR RAM.
2. To build the "boot" example with debugger support (CONFIG=Nexys4DebugConfig make boot) and program the FPGA. Then try to load Linux image from SD card or Ethernet.
In the first case, Linux starts to boot but then crashes at start-up with the following output.
[ 8.880000] a2 j 0000000001000000 a3 : ffffffff78014000 a4 : 0000000000000ff0
[ 8.880000] a5 : 0000000000001000 a6 : 0000000000000020 a7 : 0000000000000000
[ 8.880000] s2 : ffffffff803ef808 s3 : ffffffff804012d8 s4 : ffffffff8040el20
[ 8.880000] s5 : 0000000000000000 s6 : ffffffff8040d4c0 s7 : ffffffff8040d4b0
[ 8.880000] s8 : 0000000000000008 s9 : 0000000000000007 slO: 0000000000000000
[ 8.880000] sll: 0000000000000000 t3 : 0000000000000006 t4 : 0000000000000037
[ 8.880000] t5 : 0000000000000000 t6 : ffffffff804113ff
[ 8.880000] sstatus: 0000000000040120 sbadaddr: 00000000000007f4 scause: 0000000000000005
[ 8.980000] —[ end trace ac2373c8d82cf95e ]—
[ 8.990000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 8.990000]
[ 8.990000] —[ end Kernel panic - not syncing: Attempted to kill init! exit code=0x0000000b
[ 8.990000]
[ 82.040000] random: nonblocking pool is initialized
While in the second case, I get he following error during compilation:
error: 'DEV_MAP__io_ext_eth__BASE' undeclared here (not in a function)
unsigned int * const eth_base = (volatile unsigned int*)((uint32_t)(DEV_MAP__io_ext_eth__BASE));
^~~~~~~~~~~~~~~~~~~~~~~~~
Makefile:67: recipe for target 'boot.riscv' failed
So can not proceed with the implementation.
Any ideas how to resolve the problem.
Thanks and regards,
Imran Wali
4 years, 11 months
Re: [hw-dev] Adding ethernet port on lowRiscv
by Dr Jonathan Kimmitt
In principle the same MAC block can run on a KC705 if you remove the RMII converter, and change the PHY clock frequency, but there is a reason why the KC705 design has not been updated in recent releases, it does not support the same trace interface, nor does it support VGA or a keyboard, and it does not help with your objective of a second Ethernet port. Each release since v0.3 has relied on some hardware features that are outside of the FPGA and Nexys4ddr specific. This is a deliberate policy because we believe most of our market consists of academic customers who want a low cost board that can be scaled up to teaching class size, rather than some board that costs thousands of US$. Of course developers who are skilled in the art of porting designs between boards can easily make use of the majority of our Verilog design with appropriate changes, and commercial adopters who use these large boards will be assumed to have the resources to carry out the porting work also.
Sent from my iPhone
> On 13 Jun 2018, at 01:28, Claire M. M. Wong <wmingming7(a)gmail.com> wrote:
>
> Thanks for the reference. Another question would be that are the MAC verilog design and the PHY driver dependent on FPGA board that we use? For instance, if I were to implement the lowriscv v0.5 on KC705 and assuming the PHY chip is also using RMII (which is actually not), I can use the same verilog file and driver (or ethernet ) without changes?
>
> Regards,
> Ming
>
>> On Wed, 13 Jun 2018, 01:04 Dr Jonathan Kimmitt, <jrrk2(a)cam.ac.uk> wrote:
>> If you consult Alex Forencich’s repository you will find solutions for a variety of PHYs. The details of where the Verilog for the MAC (media access controller) came from are covered in the docs. There may well be a solution for RGMII. I would say the adaptation was of intermediate difficulty.
>>
>> Sent from my iPhone
>>
>>> On 12 Jun 2018, at 18:52, Claire M. M. Wong <wmingming7(a)gmail.com> wrote:
>>>
>>> In your opinion, do you think there would be a lot of changes required in the Verilog files if the PHY chip is RGMII interface?
>>>
>>>> On Wed, Jun 13, 2018 at 12:38 AM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk> wrote:
>>>> It should be adaptable to different PHYs but the verilog would have to be changed unless the chip is also RMII (reduced media independent interface)
>>>>
>>>> Sent from my iPhone
>>>>
>>>>> On 12 Jun 2018, at 18:32, Claire M. M. Wong <wmingming7(a)gmail.com> wrote:
>>>>>
>>>>> The driver lowrisc_100MHz is specific for that LAN8720 - Ethernet PHY chip only?
>>>>>
>>>>>> On Fri, Jun 8, 2018 at 3:18 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk> wrote:
>>>>>> You can find specifications of the PHY in the Digilent schematics on their website for this board. Essentially it needs to be RMII and default to 100-baseT full duplex. Of course you can also modify our Verilog design to suit a different PHY, but this is a more advanced task.
>>>>>>
>>>>>> With different PMOD, you might need to write a new driver.
>>>>>>
>>>>>> Sent from my iPhone
>>>>>>
>>>>>>
>>>>>>
>>>>>>> On 8 Jun 2018, at 08:57, Claire M. M. Wong <wmingming7(a)gmail.com> wrote:
>>>>>>>
>>>>>>> Dear Jonathan
>>>>>>>
>>>>>>> Thanks for the reply. How do I check the specification of the existing PHY?
>>>>>>> Also if other Ethernet PMOD (with completely different interface) are used, we need to find it's linux driver?
>>>>>>>
>>>>>>> Regards
>>>>>>> Claire
>>>>>>>
>>>>>>>> On Fri, Jun 8, 2018 at 2:44 PM, Dr Jonathan Kimmitt <jrrk2(a)cam.ac.uk> wrote:
>>>>>>>> Dear Claire,
>>>>>>>> You would need a PMOD with a second PHY which is compatible with our driver. I am not aware of any such, and since the PHY uses a 50 MHz clock, it might be ruled out on electronic signal quality grounds. There are Ethernet PMODs using a completely different interface but we can give no support for such usage as we never investigated this.
>>>>>>>>
>>>>>>>> Sent from my iPhone
>>>>>>>>
>>>>>>>> > On 8 Jun 2018, at 00:51, Claire M. M. Wong <wmingming7(a)gmail.com> wrote:
>>>>>>>> >
>>>>>>>> > The latest version of lowriscv v0.5 support ethernet connection to the riscv processor. Supposed that Im using Nexus DDR board and I would like to add on additional ethernet port (via pmod), would it be possible? How do I go about with the linux driver to support such connectivity?
>>>>>>>> >
>>>>>>>> > --
>>>>>>>> > You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
>>>>>>>> > To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+unsubscribe(a)groups.riscv.org.
>>>>>>>> > To post to this group, send email to hw-dev(a)groups.riscv.org.
>>>>>>>> > Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
>>>>>>>> > To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/10be6d9d-b6ed....
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> Regards,
>>>>>>> Ming
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> Regards,
>>>>> Ming
>>>
>>>
>>>
>>> --
>>> Regards,
>>> Ming
4 years, 11 months
Re: [hw-dev] Adding ethernet port on lowRiscv
by Dr Jonathan Kimmitt
Dear Claire,
You would need a PMOD with a second PHY which is compatible with our driver. I am not aware of any such, and since the PHY uses a 50 MHz clock, it might be ruled out on electronic signal quality grounds. There are Ethernet PMODs using a completely different interface but we can give no support for such usage as we never investigated this.
Sent from my iPhone
> On 8 Jun 2018, at 00:51, Claire M. M. Wong <wmingming7(a)gmail.com> wrote:
>
> The latest version of lowriscv v0.5 support ethernet connection to the riscv processor. Supposed that Im using Nexus DDR board and I would like to add on additional ethernet port (via pmod), would it be possible? How do I go about with the linux driver to support such connectivity?
>
> --
> You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+unsubscribe(a)groups.riscv.org.
> To post to this group, send email to hw-dev(a)groups.riscv.org.
> Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/10be6d9d-b6ed....
4 years, 12 months
Problem running a debug session on FPGA
by Imran Wali
Hi,
I am trying to run a debug session on FPGA as described on http://www.lowrisc.org/docs/debug-v0.3/fpga/.
After programming the nexys4ddr board with the provided debug enabled FPGA bitstream, following error is encountered while trying to open the debug daemon:
$ opensocdebugd uart device=/dev/ttyUSB1 speed=12000000
Open SoC Debug Daemon
Backend: uart
opensocdebugd: ../../src/regaccess.c:60: osd_reg_read16: Assertion `packet[0] == 3' failed.
Aborted (core dumped)
$
Could you please identify what's going wrong here.
Thanks,
Imran Wali
5 years