upgrading lowrisc sd/mmc to eMMC (and SPI)
by Luke Kenneth Casson Leighton
http://libre-riscv.org/shakti/m_class/sdmmc/
ok so i am talking to rudolf from asics.ws, and for the shakti m_class
core it needs to have eMMC. would it be of interest to lowRISC to
have eMMC (8-bit SD/MMC), and if so would the CIC behind lowRISC be
interested to share the development cost for rudolf's time?
if yes i can specifically ask him to start from ethernet-v0.5 (or
other suitable branch). i may ask him that anyway as it's likely the
easiest (libre-licensed) stack to work with.
l.
p.s. there *is* a linux kernel driver for the sd/mmc interface, right?
:) it doesn't have to be absolutely up-to-date / mainline, it just
has to "work".
5 years
updating first bootloader
by Jawad Haj-Yahya
Hello,
I would like to update the first bootloader that is being loaded into the
boot rom, could you please help me with how we can do it?
Best,
Jawad Haj-Yahya
5 years
Boot sequence of lowrisc
by Jawad Haj-Yahya
Hello,
We are trying to understand the boot sequence of lowrisc, there is some
documentation that appears at the below link, but could we could not find
where this process is implemented at the source code. Could you please help
us in pointing which source code/files (CHISEL or verilog) implements the
flow of the reset sequence as described at the below lowrisc link:
http://www.lowrisc.org/docs/untether-v0.2/bootload/
Best,
Jawad Haj-Yahya
5 years, 1 month
lowrisc v0.5 - need help to change sd card from 3.3V to 1.8V
by Anup Kini
Hi All,
I am currently running the bare-metal selftest example.
I get the following response:
selftest> D
sdhci_minion_hw_reset();
sdhci_minion_hw_reset();
*Power = 3.3V*
Card clock disabled
Trying clock div = 255
Actual clock divider = 255
Card clock disabled
Trying clock div = 255
Actual clock divider = 255
Card clock enabled
cmd timeout
...
sd_cmd_response[38:7]:00000000
sd_cmd_response[70:39]:00000000
sd_cmd_response[102:71]:00000000
sd_cmd_response[133:103]:00000000
sd_cmd_wait:00000000
sd_status:00000200
sd_cmd_packet[31:0]:00000000
sd_cmd_packet[47:32]:00000000
sd_data_wait:00000000
sd_transf_cnt:00000000
sd_detect:00000000
sd_xfr_addr:00000000
sd_align:00000000
clock_divider_sd_clk:00000000
sd_cmd_arg:00000000
sd_cmd_i:00000000
{sd_data_start,sd_cmd_setting[2:0]}:00000000
sd_cmd_start:00000000
{sd_reset,sd_clk_rst,sd_data_rst,sd_cmd_rst}:00000000
sd_blkcnt:00000000
sd_blksize:00000000
sd_cmd_timeout:00000000
cmd timeout
... the above set is repeated infinitely.
In the current configuration, SD Card interface is running at 1.8V
(LVCMOS18).
When can update this change ?
I did go through the minion_helper.c -> sdhci_write() function.
The second parameter, val carries different values, but I am unable to
figure out the main header to update this change.
Thanks & Regards,
Anup Kini.
5 years, 1 month
timing violation - eth_i and processor clock - lowrisc v0.5 port to V2000T device.
by Anup Kini
Hi All,
I am trying to port the lowrisc v0.5 design to a custom V2000T device
System Details:
Vivado 2015.4
lowrisc v0.5 release
Ubuntu 16.04 LTS
I have made the following changes to the clocks that are generated in the
design,
- 200 MHz to MIG, which generates a 100 MHz mig_ui_clk
- MIG additional clock 0 - 25 MHz for the processor core (assigned to wire
*clk*)
- MIG additional clock 1 - 200 MHz for peripheral core psoc wire
*clk_200MHz*
- Modified the axi_clock_converter_0 clk_conv to 1:4 to match the 25 MHz
processor input.
- clk_wiz_0 clk_gen generates the following
- clk_out_1 - 60 MHz for wire *clk_io_uart*
- clk_out_2 - 50 MHz for wire *clk_rmii*
- clk_out_3 - 50 MHz for wire *clk_rmii_quad*
- I have removed the connection for pxl_clk, since I will not be using VGA
or keyboard mouse.
During place design, I get the following timing violation:
Slack (VIOLATED) : -5.551ns (arrival time - required time)
Source: eth_i/open/gmii_tx_inst/gmii_tx_en_reg_reg/C
(rising edge-triggered cell FDRE clocked by
clk_out2_clk_wiz_0 {rise(a)0.000ns fall(a)10.000ns period=20.000ns})
Destination: eth_i/open/tx_enable_dly_reg[2]/R
(rising edge-triggered cell FDRE clocked by
mmcm_clkout0 {rise(a)0.000ns fall(a)20.000ns period=40.000ns})
Path Group: mmcm_clkout0
Path Type: Hold (Min at Slow Process Corner)
Clock Domain Crossing: Inter clock paths are considered valid unless
explicitly excluded by timing constraints such as set_clock_groups or
set_false_path.
Kindly let me know if I have gone wrong in any of the clock settings or If
this path has to be given set_false_path constraint.
I have not attached the entire timing report in this mail. Let me know if
that is required.
Thanks & Regards,
Anup Kini.
5 years, 1 month
