need help with dram test - untether - v0.2
by Anup Kini
Hi All,
I was able to successfully port the untethered design to a custom Virtex 7
2000T device.
I also ran the hello world example, which ran successfully.
When I try to run the dram test, the print stops after the 1st msg:
DRAM test program.
Write block @0 using key 0
I did a little debugging and added a print step inside the dram.c code,
line: 57, inside the for loop.
It gets stuck at step 8 (i.e i iterated 8 times.)
SetUp details:
Vivado 2015.4
Virtex 7 2000T - xc7v2000tflg1925-1
lowrisc - untether v0.2
MIG UI Clock @ 100 MHz
Uart, BRAM, SPI-SD, Core - all running at 25 MHz
I have configured the axi_clock_convertor to 1:4 ratio for the above clock
setting.
Kindly let me know how to proceed debugging this issue further.
Thanks & Regards,
Anup Kini.
5 years, 10 months
dii_package not declared - KC705 build
by Anup Kini
Hi All,
I cloned a fresh copy of ethernet-v0.5 today and tried to build for KC705.
I get the following errors during the synthesis process.
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device
'xc7k325t'
ERROR: [Synth 8-1031] dii_package is not declared
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:3]
ERROR: [Synth 8-1766] cannot open include file consts.vh
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:5]
ERROR: [Synth 8-1766] cannot open include file dev_map.vh
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:6]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_MEM_TAG_WIDTH
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:195]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_PADDR_WIDTH
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:196]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_MEM_DAT_WIDTH
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:197]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_IO_TAG_WIDTH
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:509]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_IO_DAT_WIDTH
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:511]
INFO: [Synth 8-2350] module chip_top ignored due to previous errors
[/home/anup/work_sumana/lowrisc-chip-ethernet-v0.5/src/main/verilog/
chip_top.sv:9]
System Config:
Ubuntu 16.04
Vivado 2015.4
lowrisc branch - ethernet-v0.5
When I change the board to nexys4_ddr, it works fine.
Kindly let me know how to include the dii_package.
Thanks & Regards,
Anup Kini.
5 years, 10 months
lowrisc 0.5 release on custom Virtex 7 2000T
by Anup Kini
Hi All,
I am trying to build the lowrisc 0.5 release for a custom Virtex 7 2000T
device.
To begin with I tried to build the nexus 4 ddr design, but the
implementation fails.
Has anyone been successfull in pulling the latest 0.5 release from github
and building it.
I have attached the vivado log in this mail.
Looking forward for any help.
Thanks & Regards,
Anup Kini.
5 years, 10 months
Will lowRISC participate in GSoC 2018?
by Denis Obrezkov
Hello,
will lowRISC participate in GSoC 2018?
I have an idea of porting xen or kvm on lowRISC. What do you think about it?
--
Regards, Denis Obrezkov
5 years, 10 months
Ethernet support for lowrisc
by Jawad Haj-Yahya
Hello,
Could you please help with instructions on how to add support for Ethernet
port to the latest lowrisc (0.4)?
Best,
Jawad Haj-Yahya
5 years, 11 months
