Re: Weekly Report of Porting musl to RISC-V Project #5
by Alan Pillay
What is the current status of musl on RISC-V?
This was the last time I heard about it, but it has been many months since.
Regards.
> Hello,
>
> Thanks to the folks, I passed the mid-term evaluation. Now it is about
> time to publish the fifth progress report on porting musl on RISC-V.
>
> Last week, the toolchain itself has been built for RISC-V and running
> on Spike, and libc-test [1] can be executed with it now. I posted the
> result of tests on [2]. The REPORT.txt file contains all error
> messages of failed tests, both run-time ones and compile-time ones.
>
> Some failures are expected since musl on x86_64 also does the same
> ones (e.g. errors in src/api/fcntl.c), but there are some unexpected
> errors too. I guess that the "warning: <the name of a header> is
> shorter than expected" warning indicates bugs in arch-dependent part
> of I/O functions or system calls (or kernel?) and it causes syntax
> errors in the same compilation unit.
>
> Moreover, some tests triggers a "signal 11" error (segmentation fault)
> in libc. I added some logs to [2]. They are bugs in the port,
> obviously. I am working on them.
>
> The good news is, anyway, some results are *better than x86_64*,
> especially in math functions :-)
> (probably the cause is the difference in the floating-point precision,
> though. it is usual in float tests...)
>
> It takes long, long time to get but finally I have a (seems-to-be)
> working test suite for the port. I will continue to debug and fix the
> port using the result. Stay tuned!
>
>
> [1]: http://nsz.repo.hu/git/?p=libc-test
> [2]: https://gist.github.com/omasanori/ee828369aea844ac7fdfdc8362953299
>
> --
> Masanori Ogino
6 years, 3 months
Interested in GSoC 2017
by Yogesh Mahajan
Hello everyone,
First of all congratulation for getting selected in GSoC 2017. I'm Yogesh
from Mumbai and pursuing my Undergraduate degree in Electrical Engineering
at IIT Bombay. I am mostly interested in hardware design than software but
can work with software section too. I have overlooked the projects
proposals for GSoC 2017 and I would like to work on open-source IPs or
CMSIS-DSP
library.
I am very comfortable with VHDL and have completed a number of small
projects as part of the curriculum as well as the hobby. Some of my recent
hardware projects are as follows:
1. Simple Multicycle RISC processor for FPGA (Complete and Tested)
2. 6 Stages Pipelined RISC processor for FPGA with UART
bootloader (Complete and Tested)
3. Superscalar RISC processor (Active)
4. Hardware abstraction layer to use ADC and DAC on FPGA/ CPLD (Complete ad
tested)
5. UART peripheral for FPGA/ CPLD (Complete and tested)
I have used Altera Cyclone IV FPGA/ MAX V CPLD for testing above projects.
So, how should I proceed for GSoC's application? Are there any extra topics
I need know before getting started?
Best regards,
Yogesh
6 years, 6 months
new Developer
by Shubham Kumar
Sir
I'm a third year Indian engineering student majoring in electronics and computer engineering looking to gain some experience in open source development. I came to know your organisation and I'm very interested in contributing to this org . Can you provide me an idea of where exactly to start since I'm new to this ?? Thanks in advance.
Regards
Shubham Kumar
6 years, 7 months
