Regarding make bitstream FPGA demo problem
by weizhong huang
Dear all,
Recently I have encountered some problems regarding FPGA DEMO generate
bitstream.
ideally,
after generating bitstream
cd $TOP/fpga/board/$FPGA_BOARD
make bitstream
The final bit stream is located at
lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit.
However, in my case, there is no such folder called impl_1
*~/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.runs$
lsaxi_bram_ctrl_0_synth_1 axi_quad_spi_0_synth_1
mig_7series_0_synth_1axi_clock_converter_0_synth_1
axi_uart16550_0_synth_1 synth_1*
and my error message after make bitstream
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
*# wait_on_run synth_1[Mon Sep 26 17:39:13 2016] Waiting for synth_1
to finish...[Mon Sep 26 17:39:47 2016] synth_1 finishedwait_on_run:
Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak =
1052.801 ; gain = 12.504 ; free physical = 995 ; free virtual = 13110#
launch_runs impl_1 -to_step write_bitstreamERROR: [Common 17-70]
Application Exception: Failed to launch run 'impl_1' due to failures
in the following
run(s):axi_uart16550_0_synth_1axi_bram_ctrl_0_synth_1mig_7series_0_synth_1axi_clock_converter_0_synth_1These
failed run(s) need to be reset prior to launching 'impl_1' again.INFO:
[Common 17-206] Exiting Vivado at Mon Sep 26 17:39:47
2016...Makefile:110: recipe for target
'lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit'
failedmake: ***
[lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit] Error 1*
There is also warning messages regarding could not locate several files
*WARNING: [IP_Flow 19-3664] IP 'axi_quad_spi_0' generated file not
found '/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0_stub.v'.
Please regenerate to continue.WARNING: [IP_Flow 19-3664] IP
'axi_clock_converter_0' generated file not found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/axi_clock_converter_0/axi_clock_converter_0_sim_netlist.vhdl'.
Please regenerate to continue.WARNING: [IP_Flow 19-3664] IP
'mig_7series_0' generated file not found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/mig_7series_0/mig_7series_0_sim_netlist.v'.
Please regenerate to continue.*
Please advise. I tried make cleanall and make bitstream several times.
Thank you for your help
Weizhong Huang
7 years
What are you working on this week?
by Dr Jonathan Kimmitt
Dear All,
I started work at Cambridge University Computer Labs on 1st July.
Since then I have implemented a patch to allow lowrisc Linux to run on
the Nexys-video boards from Digilent. This is beneficial because the
FPGA has around double the CLBs and 4 times the amount of DDR memory.
However it has other changes which are not so beneficial, for example
the UART lacks flow control which is a problem for the debugging
sub-system and the Ethernet PHY interface is incompatible with
Nexys4-ddr. The DDR interface is DDR3 instead of DDR2 so it needs a 4:1
instead of 2:1 clock rate conversion. The status of this board is
uncertain going forward now, meanwhile I have started work on the Minion
I/O subsystem which will most likely use an adapted Pulpino processor,
though other candidates are possible.
A related task is cleaning our database of proprietary Xilinx IP so that
we can make a design which is suitable for the forthcoming tape out, and
removing deprecated techniques such as latches from the designs. Because
of the extra logic and routing for the Minion sub-system it will be
limited to running on the XC705 for now, however working with the Minion
system on its own is possible on our standard boards.
Regards,
Jonathan
7 years
Re: [lowrisc-dev] What are you working on this week?
by Alex Bradbury
On 5 Sep 2016 08:22, "Hesham Almatary" <heshamelmatary(a)gmail.com> wrote:
> This week I am going to thoroughly read the CHERI manual (CL-TR-981)
> again to implement the expected behavior of the two instructions.
> After this, I will continue adding more instructions, which will be
> relatively easier.
Thanks for kicking off the thread this week Hesham, sounds like interesting
stuff.
Last week our interns at the lab finished up their work, so I've spent
some time proof reading their write up. We hope to get that posted soon.
The Computer Lab also played host to an OpenBSD hackathon which led to some
interesting discussions regarding defenses against code reuse attacks like
ROP. The addition of support for execute-only pages in 1.9 of the
privileged spec will be good to explore.
I'm running the LLVM Cauldron in Hebden Bridge on Thursday so it may not be
a particularly productive week otherwise. I will continue to work on risc-v
llvm codegen.
Alex
7 years
change of baud rate for the trace debugger release
by Wei Song
Hello,
This is a notice for the recent changes in the debug-v0.3 release.
The default baud rate for the trace debugger connection to FPGA is
increased from 3M to 12M.
This significantly reduces the time for downloading images to FPGA and
hopefully reduces the probability of trace overflow.
The tutorial has been changed accordingly. Code has already been updated
in the master and debug-v0.3 branches.
The pre-compiled images will be updated today.
Thanks to Stefan for this improvement.
Other changes you may like to know:
It is now able to mount the SD card inside the RISC-V Linux.
The on-board Flash is connected and can be used in execution in place
(XIP) mode as a ROM.
Extra control logic to the SPI interface is added hopefully to increase
the comparability for various SD cards.
All changes has been mentioned in the tutorial accordingly.
Best regards,
Wei
7 years
What are you working on this week?
by Hesham Almatary
Hi,
Last week, I got ccall and csetoffest CHERI instructions added to
RISC-V binutils, as the first two instructions with their expected
arguments, tested with as, objdump and ld. Then I added support to
spike to recognize the CHERI extension and enable it on run-time
(spike --extension=cheri) same as dummy_rocc (rocket custom
co-processor). Now that spike has its own CHERI co-processor base, it
can recognize CHERI instructions (tested with ccall and csetoffset).
This week I am going to thoroughly read the CHERI manual (CL-TR-981)
again to implement the expected behavior of the two instructions.
After this, I will continue adding more instructions, which will be
relatively easier.
Cheers,
--
Hesham
7 years
[GSoC] Arduino Libraries Porting is Ready
by Mahmoud Elmohr
Hi everyone,
Sorry for not being updating with my status, as my project for GSoC I have
successfully ported Arduino libraries (the core libraries and peripherals )
and everything is now published on Github:
https://github.com/pulp-platform/pulpino
Now we can use Arduino functions with PULPino which has the potential to
act as the minion cores for lowRISC, such libraries would make it easy to
use the peripherals without great effort and would gain from the Arduino's
community.
The upcoming phase would be to port the Arduino IDE too to have the same
features that Arduino users are used to.
If anyone has any feedback or ideas, it would be my pleasure to hear.
Regards
Mohr
7 years
