Re: Weekly Report of Porting musl to RISC-V Project #5
by Alan Pillay
What is the current status of musl on RISC-V?
This was the last time I heard about it, but it has been many months since.
> Thanks to the folks, I passed the mid-term evaluation. Now it is about
> time to publish the fifth progress report on porting musl on RISC-V.
> Last week, the toolchain itself has been built for RISC-V and running
> on Spike, and libc-test  can be executed with it now. I posted the
> result of tests on . The REPORT.txt file contains all error
> messages of failed tests, both run-time ones and compile-time ones.
> Some failures are expected since musl on x86_64 also does the same
> ones (e.g. errors in src/api/fcntl.c), but there are some unexpected
> errors too. I guess that the "warning: <the name of a header> is
> shorter than expected" warning indicates bugs in arch-dependent part
> of I/O functions or system calls (or kernel?) and it causes syntax
> errors in the same compilation unit.
> Moreover, some tests triggers a "signal 11" error (segmentation fault)
> in libc. I added some logs to . They are bugs in the port,
> obviously. I am working on them.
> The good news is, anyway, some results are *better than x86_64*,
> especially in math functions :-)
> (probably the cause is the difference in the floating-point precision,
> though. it is usual in float tests...)
> It takes long, long time to get but finally I have a (seems-to-be)
> working test suite for the port. I will continue to debug and fix the
> port using the result. Stay tuned!
> : http://nsz.repo.hu/git/?p=libc-test
> : https://gist.github.com/omasanori/ee828369aea844ac7fdfdc8362953299
> Masanori Ogino
5 years, 9 months
low-risc on Xilinx FPGA
by Brad Walker
I've noticed there is a port, with bitstreams, of the Low-Risc processor to
the Nexy Artix-7 FPGA board.
Has anyone done any work to get the processor instantiated on the Xilinx
Zynq family (i.e. Zedboard/Microzed) of FPGAs?
ps: BTW, Keep up the great work!
6 years, 2 months