Introducing phab.lowrisc.org
by Alex Bradbury
Hi all,
I've set up a Phabricator instance at http://phab.lowrisc.org/. The
intent is to better keep track of issues and to better share ideas and
progress with the wider community. Consider it 'beta' for now, and any
suggestions on making best use of it and organisation are most
welcome. You should be able to log in with a Github account. Please do
start kicking the tires and help filling out relevant issues.
For those not familiar with Phabricator, it is a collaboration tool
that originally came out of Facebook
<http://en.wikipedia.org/wiki/Phabricator>. I'll happily declare that
it "sucks less" than the other available bug tracking or collaboration
solutions out there.
* Why not Github issues? We have no control over the proprietary
Github platform, and hope to keep track of issues across a wide range
of projects while being searchable from one place.
* Why not report issues directly upstream? For straight-forward bugs
with a non-lowRISC upstream they should be reported to the appropriate
bug-tracker (and ideally tracked on the lowRISC phabricator as well).
However, there's also the need to keep track of feature requests or
lowRISC-specific issues, and the policy of the upstream bugtracker may
not welcome such issues.
* A hope is that the phabricator will keep track of feature requests,
providing a useful starting point for people wanting to contribute.
See also http://phab.lowrisc.org/T3
* In time, I expect we will extend our use of Phabricator to use the
code review components, as used successfully by LLVM, FreeBSD, and
others
All feedback very welcome,
Alex
8 years, 6 months
[GSoC 2015] Introduction - Porting jor1k to RISC-V
by Prannoy Pilligundla
Hello Everyone,
I am Prannoy and I am a pre-final year undergrad student at BITS-Pilani,
India. I will be working on "Porting jor1k to RISC-V" as a part of Google
Summer of Code 2015. I am extremely honoured for having been selected. I
would like to thank the community for having faith in me and I promise to
put in my best efforts during the course of the project. I had successfully
completed Google Summer of Code 2014 with LyX. Also, congratulations to all
others who are participating in this year's Summer of Code.
jor1k is currently built for OpenRISC (OR1K Specification) and my main task
would be to port it for RISC-V. My first goal would be to boot Linux
successfully. Then I am planning to work on implementing more features like
providing a web interface to test the compiled binaries, providing a demo
file system with some major tools, compiling the Linux kernel with the
drivers of the devices currently supported by jor1k, adding support to
features of lowRISC such as minion cores etc. Initially my plan is to focus
on booting Linux using a not-so-fast implementation taking safecpu.js [1]
as the reference. Then I plan to optimize the speed by working on
implementing an asm.js optimized version like in fastcpu.js [2] where the
number of lines of code executed per instruction is reduced to a minimum.
After I am done booting Linux via the optimized version, I will go on to
implement the other features.
Looking forward to comments and suggestions from your side.
Thanks and Regards
Prannoy Pilligundla
[1] https://github.com/s-macke/jor1k/blob/master/js/worker/or1k/safecpu.js
[2] https://github.com/s-macke/jor1k/blob/master/js/worker/or1k/fastcpu.js
8 years, 6 months
GSoC'15 - Porting seL4 to RISC-V - Introduction
by Hesham ALMatary
Hi all,
I was fortunate enough to be accepted in this year's GSoC instance
with "Porting seL4 to lowRISC" project for lowRISC organization. My
name is Hesham, and I am a PhD student at the University of York and
my mentor is Stefan Wallentowitz.
As the name of the project indicates, it's about porting the formally
verified seL4 microkernel [1] to RISC-V/lowRISC platform. Initially,
I'll work on getting the seL4 microkernel working on Spike simulator
which currently supports both 32-bit and 64-bit modes. Then we can
move to running it on real hardware (Rocket Chip [2]). The project
will extensively make use of the newly published privileged spec [3]
and will study how to utilize the current 4 RISC-V modes (though
there's no implementation for hypervisor mode yet). Some of the
user-level libraries/applications will also be nice to port.
I'd appreciate any comments or suggestion that may help with this project.
[1] http://sel4.systems/
[2] https://github.com/ucb-bar/rocket-chip
[3] http://riscv.org/download.html#tab_spec_privileged_isa
Thanks,
--
Hesham
8 years, 6 months
GSoC 2015 : An online Verilog IDE based on YosysJS
by Baptiste Duprat
Hello !
My name is Duprat Baptiste and I am an accepted student for Google Summer of Code 2015 ! I come from the University of Paris Sud. I study Electrical and Computer Engineering. Currently I am in a student exchange program (Erasmus) at the Transylvania University of Brasov, Romania. I am in Brasov for one semester and I have to admit that Erasmus is pretty nice. Brasov is a beautiful city and courses are interesting. It is my first mail in this mailling list since I was directly in contact with my mentor, Clifford Wolf.
My project is to design and build an online Verilog IDE based on YosysJS. Yosys is a framework for Verilog RTL synthesis made by Clifford Wolf. YosysJS is a JavaScript port of Yosys done with Emscripten. My work is to display the generated netlist and place correctly the logic gates. After that, I will have to work on simulations. We will have the ability to evaluate the circuit with given input values. And finally, I will have to build an application that integrate the previous work. Do not hesitate to ask me any questions, I will be happy to answer them.
I am really excited about Google Summer of Code and I hope that this summer will be perfect !
Sincerely,
Baptiste Duprat
8 years, 6 months
SoC 2015 - Implement a Wishbone to TileLink bridge and extend TileLink documentation
by Tom Repetti
Hello everybody,
My name is Tom, and I am very fortunate to have the chance to work with my
advisor Wei Song and the rest of the lowRISC team on an exciting digital
design problem this summer, and I truly appreciate the generous sponsorship
of the lowRISC project to support the work. My task for the summer will be
building a protocol bridge between the TileLink interconnect fabric used in
the UCB Rocket chip implementation (
http://www.lowrisc.org/docs/tutorial/rocket-chip/) of the RISC-V
architecture and the well-established Wishbone interconnect standard (
http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29). I am just now
finishing up my master's degree at Brown University in Providence, RI USA
and will be starting a PhD at Columbia University in New York, NY USA this
fall, and I feel this is the perfect opportunity to get involved in a
promising open source hardware project like lowRISC.
I'm going to be designing a protocol bridge in Verilog to be wrapped in
Scala and interfaced with the rest of the lowRISC Chisel (
https://chisel.eecs.berkeley.edu/) design that will allow for access to
memory mapped Wishbone peripherals from the TileLink interconnect. If all
goes according to plan, and if I am thorough in designing the testbenches
and checking all the edge cases, we will be able to use many of the open
source IP cores available thanks to the many years of hard work of members
of the opencores.org community. There are a variety of immediately useful
cores within the ecosystem that have been implemented with the Wishbone
spec and have already been verified in both ASIC and FPGA environments,
including SD card controllers, ethernet MACs, and a variety of serial and
wire protocol controllers, and I'm looking forward to testing a couple of
them under RISC-V Linux on an FPGA dev board once the bridge is up and
running.
Let me know if you have any questions or suggestions. Looking forward to
getting to know everyone better once we all get underway.
Best wishes,
Tom
8 years, 6 months
SoC 2015 - Extend Tavor to support generation of assembly test cases - Introduction
by Yoann Blein
Hi everyone,
My name is Yoann, I'm a second year Master's student at Ensimag (Grenoble -
France). I'm very grateful that lowRISC offered to sponsor ma participation in
the project this summer. I'm working on the "Extend Tavor to support directed
generation of assembly test cases" project.
Briefly, the goal of the project is to extend the fuzzing tool Tavor [1] so
that it allows specifying an instruction set. From this specification, we
should be able to automatically derive a comprehensive test suite, covering
many corner cases. The test suite can be used to perform acceptance testing on
the implementation of an ISA (rv64 here). It can also be used to ensure that an
implementation behaves properly by comparing the test results we another
reference implementation (e.g., hardware vs software implementation). Tavor has
a fresh Go codebase that should be fun to work with.
Feel free to get in touch for any comments or questions.
[1] https://github.com/zimmski/tavor
Best,
--
Yoann
8 years, 6 months
Summer of Code Introduction: TCP offload using rump kernels
by Sebastian Wicki
Hi all,
I'm also honored to participate in this years lowRISC Summer of Code,
where I will implement TCP offloading to the lowRISC minion cores
using rump kernels. My name is Sebastian and I'm a second year
Master's student at the Swiss Federal Institute of Technology in
Zurich (ETH Zurich).
As part of this project, I will port rump unikernels [1] to bare-metal
RISC-V and implement an interface for communicating with the rump
kernel on the minion core. The rump kernel project is highly portable
collection of drivers and libraries based on NetBSD. This enables
applications to make use of this infrastructure without the overhead
of a full-blown operating system. The goal of the project is to use
rump kernels to offload TCP/IP processing to minion cores. If
successful, the same approach could be used for other devices as well.
My mentor is Justin Cormack.
Feel free to ping my for any comments or questions, I'm gandro on IRC.
Regards,
Sebastian
[1] http://rumpkernel.org/
8 years, 7 months