GSoC15: Rump kernels on minion cores
by Sebastian Wicki
Hi
It seems customary to introduce oneself as a aspirant for GSoC to the
mailing list, so hello, I'm Sebastian :) I already contacted Justin
Cormack about this, I am interested in porting rump kernels to the
minion cores for the purpose of TCP/IP offloading. The proposal can be
found on Google Melange [1].
While there are lots of great information on rump kernels on the web,
I was wondering if there is some more content on the whole minion core
concept, e.g. technical specifications, emulators and so on. This
would help me a lot, as the proposal submitted for the deadline is
rather generic.
So far, the only thing I have found is the document [2] on the lowRISC
page. Any hints or pointers on this are highly appreciated.
Cheers,
Sebastian Wicki
[1] https://www.google-melange.com/gsoc/proposal/review/student/google/gsoc20...
[2] http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/
8 years, 5 months
GSoC: Open FPGA toolchain
by Matthias Bock
Hi,
Like the ones before me, I would like to use the
opportunity to introduce myself to this list:
I am a programmer, C and Python mostly, and
in this year's GSoC applied for lowRISC's
project on establishing an open source
toolchain/workflow around Lattice's iCE40
series of FPGAs. I'm a big fan of FPGA development
(although I started tinkering with them only about
half a year ago) and very much see the need for
completely FOSS tools for FPGA development.
Also, I have worked with the <svg> HTML element,
in the BooleSim project:
http://matthiasbock.github.io/BooleSim
so I have a little experience with JavaScript/HTML5,
which I would be happy to share with the aspirant
of the Schematic Netlist Viewer project.
It would be great, if you could let me know,
what you think about my proposal.
Best, Matthias
8 years, 5 months
GSOC 2015 - Proposal
by Rahul Behl
Hi,
I'd like to work on the 'Adding support for coverage collection in Cocotb'
idea for GSoC 2015. Owing to my previous discussions with Chris (CC'ed in
the mail) have come up with a draft for the proposal. You can find it
here -
https://www.google-melange.com/gsoc/proposal/review/student/google/gsoc20...
Any suggestions and feedback are welcome.
Cheers!
--
*Rahul Behl, *BE(Hons) Electronics & Instrumentation Engineering
*Birla Institute of Technology & Science,* Pilani
KK Birla Goa Campus
8 years, 6 months
GSOC 2015
by Pankaj Kumar
My name is Pankaj and i am a BCA student .
I would like to work on adding chisel support to fusesoc this summer
after my exams are over by april
I am not experienced with python but first few lessons make it seem easy.
How should chisel integration be done
for start we could just add code to fuse soc to run chisel as
subprocess with programed argument but i dont think thats sufficient .
As i under stand chilsel run on jvm
multple ways to glue together python and java/Scala code
https://wiki.python.org/moin/IntegratingPythonWithOtherLanguages#Java
8 years, 6 months
Re: Feedback for GSoC 2015 proposal - Schematic Viewer for Netlists
by Keheliya Gallaba
Hi Clifford,
Thank you very much for the feedback.
Best Regards,
Keheliya
On Fri, Mar 27, 2015 at 5:41 AM, Clifford Wolf <clifford(a)clifford.at> wrote:
> On Thu, Mar 26, 2015 at 03:28:29PM -0700, Keheliya Gallaba wrote:
>> I'd like to work on the 'Schematic Viewer for Netlists' idea for GSoC
>> 2015 and have come up with a draft for the proposal. You can find it
>> here[1]. I will be very thankful if you can have a look at it and
>> provide me with feedback. Specially if I need to expand further on
>> implementation details and the timeline, please let me know.
>
> your proposal looks very good. I especially like that you have worked on
> gephi and graphviz before and that you have made some research on existing
> libraries. I also like that you plan to implement an end-to-end solution
> first and then extend it to cover all the features.
>
8 years, 6 months
Re: [lowrisc-dev] Introduction : GSOC 2015 : Accessing the OpenCores ecosystem
by gurshaant malik
Hi,
I had my Mid-Semester exams at my university. Sorry for the lapse in
communication during this time. So, here are the updates from my side :
---------------------------------------------------------------------------------------------------------------------------
1.)As asked by Olof Kindgren, I have setup the entire toolchain and
generated the waveforms which are attached. I used gtkwave
<http://gtkwave.sourceforge.net/> to study the waveform. The waveform is
attached. The weird thing is I get vcd2vpd not found. I tried if there was
any way to install it but I could not find any.I have attached the images
of the waveforms I captured.
----------------------------------------------------------------------------------------------------------------------------
2.) I have also generated the FPGA synthesizable verilog. The verilog
files are also attached.
----------------------------------------------------------------------------------------------------------------------------
3.) I have also generated the VLSI synthesizable verilog. The verilog files
are also attached.
All the progress(Waveforms, FPGA verilog, VLSI Verlog) so far can be
downloaded from here
<https://drive.google.com/file/d/0B4ECbn27RRaaOXN6NkZ3VmdSeDA/view?usp=sha...>
-----------------------------------------------------------
----------------------------------------------------------------
4.) I have pushed my miscellaneous work in FPGA related fields to my github
<https://github.com/GurshaantMalik/Robotics_FPGA>. Most of these
codes/designs are in the fields of Robotic Algorithms. Please note that
this is a very small fraction of work done by me as my research work is
confidential for the moment as it has been submitted to a Research
Conference. If you want, I am willing to send it to you in private for
review.
-----------------------------------------------------------------------------------------------------------------------------
5.) I have started working on the proposal for the project. The document is
still in a rough stage. I am trying to push through it as quickly as
possible. I will send you all a first draft for review very very soon.
------------------------------------------------------------------------------------------------------------------------------
6.)Also, here is a brief description of work done/ profile :
*XILINX - **SYSTEMS INTERN**( 6 Months ):*
1.) Actively involved in development, validation, cross-development of the
next generation of Xilinx Ultra-Scale Zynq architecture. (More Info
<http://finance.yahoo.com/news/xilinx-stays-generation-ahead-16nm-12000020...>
).
2.) Involved in development and validation of multiple Sub Systems of the
Zynq Family that included design, timing closure and validation. The IPs
were both hard and soft. Some of the IPs I worked on were : SGMII
<http://www.xilinx.com/support/documentation/ip_documentation/gig_eth_pcs_...>
, DRP-MMCM
<http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1...>
, CAN <http://www.xilinx.com/products/intellectual-property/do-di-can.html>
etc.
3.) Writing cross-platform scripts for Error Correction Codes for
generating OCM for .elf uses.
*RENIAC - FPGA DESIGN INTERN( 1 Year):*
1.) Creating high speed data pipelines with matched timing requirements.
2.) Creation of testbenchs and example designs for simulation and real time
testing of hardware.
3.) Exposure to front and back end design flows including netlist generation
4.) Writing Tcl scrips centred around automation of project creation and
simulation
*MS By Research (Current) :*
I work in the field of FPGA based Robotics. I am currently working in the
field of parallelizing RRT (Randomly exploring Random Trees), an
exploration algorithms for Robotic designs with complex degree of freedom
and computationally intensive inverse kinematics. For this purpose, 2
architectures were created, both of which are listed below :
1.)Created an FPGA based 2D Hybrid Memory array that amalgamates
distributed memory's Data Integrity with shared memory's low data flow
latency. Used this array to completely parallelize RRT-an exploration
algorithms for Robotic designs with complex degree of freedom and
computationally intensive inverse kinematics.[*SUBMITTED TO ROBOTICS
CONFERENCE(CONFIDENTIAL)*] .
2.) For a system consisting of N parallel systems that want to access the
same memory, the worst constraint being randomness and concurrent
read/write, a combinatorial architecture was designed that allowed for all
the 2^N cases of random access with 0 scheduling time, allowing for
ultra-fast write/read times .
------------------------------------------------------------
--------------------------------------------
Also, I would again like to apologize for the lapse in communication during
my exams. If you have any more suggestions/ critiques, please let me know.
I would be more than happy to work on it :)
Cheers,
Gurshaant
On Tue, Mar 24, 2015 at 1:20 AM, gurshaant malik <garymalik8080(a)gmail.com>
wrote:
> Hi,
>
> I had my Mid-Semester exams at my university. Sorry for the lapse in
> communication during this time. So, here are the updates from my side :
>
>
> ---------------------------------------------------------------------------------------------------------------------------
>
> 1.)As asked by Olof Kindgren, I have setup the entire toolchain and
> generated the waveforms which are attached. I used gtkwave
> <http://gtkwave.sourceforge.net/> to study the waveform. The waveform is
> attached. The weird thing is I get vcd2vpd not found. I tried if there was
> any way to install it but I could not find any.I have attached the images
> of the waveforms I captured.
>
> ----------------------------------------------------------------------------------------------------------------------------
> 2.) I have also generated the FPGA synthesizable verilog. The verilog
> files are also attached.
>
> ----------------------------------------------------------------------------------------------------------------------------
> 3.) I have also generated the VLSI synthesizable verilog. The verilog
> files are also attached.
>
> ---------------------------------------------------------------------------------------------------------------------------
> 4.) I have pushed my miscellaneous work in FPGA related fields to my
> github <https://github.com/GurshaantMalik/Robotics_FPGA>. Most of these
> codes/designs are in the fields of Robotic Algorithms. Please note that
> this is a very small fraction of work done by me as my research work is
> confidential for the moment as it has been submitted to a Research
> Conference. If you want, I am willing to send it to you in private for
> review.
>
> -----------------------------------------------------------------------------------------------------------------------------
> 5.) I have started working on the proposal for the project. The document
> is still in a rough stage. I am trying to push through it as quickly as
> possible. I will send you all a first draft for review very very soon.
>
> ------------------------------------------------------------------------------------------------------------------------------
> 6.)Also, here is a brief description of work done/ profile :
>
> *XILINX - **SYSTEMS INTERN**( 6 Months ):*
>
> 1.) Actively involved in development, validation, cross-development of
> the next generation of Xilinx Ultra-Scale Zynq architecture. (More Info
> <http://finance.yahoo.com/news/xilinx-stays-generation-ahead-16nm-12000020...>
> ).
>
> 2.) Involved in development and validation of multiple Sub Systems of the
> Zynq Family that included design, timing closure and validation. The IPs
> were both hard and soft. Some of the IPs I worked on were : SGMII
> <http://www.xilinx.com/support/documentation/ip_documentation/gig_eth_pcs_...>,
> DRP-MMCM
> <http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1...>,
> CAN <http://www.xilinx.com/products/intellectual-property/do-di-can.html>
> etc.
>
> 3.) Writing cross-platform scripts for Error Correction Codes for
> generating OCM for .elf uses.
>
>
>
> *RENIAC - FPGA DESIGN INTERN( 1 Year):*
> 1.) Creating high speed data pipelines with matched timing requirements.
>
> 2.) Creation of testbenchs and example designs for simulation and real
> time testing of hardware.
>
> 3.) Exposure to front and back end design flows including netlist
> generation
>
> 4.) Writing Tcl scrips centred around automation of project creation and
> simulation
>
> *MS By Research (Current) :*
>
> I work in the field of FPGA based Robotics. I am currently working in the
> field of parallelizing RRT (Randomly exploring Random Trees), an
> exploration algorithms for Robotic designs with complex degree of freedom
> and computationally intensive inverse kinematics. For this purpose, 2
> architectures were created, both of which are listed below :
>
> 1.)Created an FPGA based 2D Hybrid Memory array that amalgamates
> distributed memory's Data Integrity with shared memory's low data flow
> latency. Used this array to completely parallelize RRT-an exploration
> algorithms for Robotic designs with complex degree of freedom and
> computationally intensive inverse kinematics.[*SUBMITTED TO ROBOTICS
> CONFERENCE(CONFIDENTIAL)*] .
>
> 2.) For a system consisting of N parallel systems that want to access the
> same memory, the worst constraint being randomness and concurrent
> read/write, a combinatorial architecture was designed that allowed for all
> the 2^N cases of random access with 0 scheduling time, allowing for
> ultra-fast write/read times .
>
> --------------------------------------------------------------------------------------------------------
>
> Also, I would again like to apologize for the lapse in communication
> during my exams. If you have any more suggestions/ critiques, please let me
> know. I would be more than happy to work on it :)
>
> Cheers,
> Gurshaant
>
> On Fri, Mar 13, 2015 at 10:35 PM, Reinoud Zandijk <reinoud(a)netbsd.org>
> wrote:
>
>> Hi Gurshaant,
>>
>> On Fri, Mar 13, 2015 at 09:55:42PM +0530, gurshaant malik wrote:
>> > g++ -O1 -std=c++11 -I/mnt/GARY/RESEARCH/GSOC15/lowRISC/TC/include
>> > -I/mnt/GARY/RESEARCH/GSOC15/lowRISC/rocket-chip/csrc
>> > -I/mnt/GARY/RESEARCH/GSOC15/lowRISC/rocket-chip/dramsim2 -include
>> > generated-src-debug/Top.DefaultCPPConfig.h -Igenerated-src-debug -c -o
>> > emulator.debug.o
>> > /mnt/GARY/RESEARCH/GSOC15/lowRISC/rocket-chip/csrc/emulator.cc In file
>> > included from
>> > /mnt/GARY/RESEARCH/GSOC15/lowRISC/rocket-chip/csrc/emulator.cc:3:0:
>> > /mnt/GARY/RESEARCH/GSOC15/lowRISC/rocket-chip/csrc/htif_emulator.h:6:32:
>> > fatal error: fesvr/htif_pthread.h: No such file or directory #include
>> > <fesvr/htif_pthread.h> ^ compilation terminated. make: ***
>> > [emulator.debug.o] Error 1
>>
>> You first have to compile and in stall the riscv-fesvr package together
>> with
>> possibly the riscv-pk (pseudo-kernel) package :) The fesvr stands for
>> FrontEndSerVeR, a program that connects to the other side of the HTIF and
>> allows the output of characters, installing binaries, reading result
>> binaries
>> etc.
>>
>> With regards,
>> Reinud
>>
>>
>
8 years, 6 months
GSoC deadline and proposal reviews
by Alex Bradbury
Hi all,
The deadline for applications for Google summer of Code is tomorrow,
Friday 27th March at 1900UTC. Please do not worry if you have
submitted a proposal and haven't yet received comments. We do have the
ability to unlock proposals to allow students to edit them after the
deadline, so there's no need to be concerned that you may not have the
chance to incorporate feedback·
Best,
Alex
8 years, 6 months
