update on untether a lowRISC SoC
by Wei Song
Hello,
Here is an update on my work on untethering a lowRISC SoC.
Progress:
branch rev:
https://github.com/lowrisc/lowrisc-chip/tree/dev
The hardware part of the initial untethered lowRISC chip is nearly finished.
A Xilinx KC705 board is used to develop the untethered SoC but low-end
development boards are scheduled to be supported once the initial code
release is ready.
Summary of current changes:
Memory mapped IO has been added using a separated uncached Tilelink.
The original Rocket HTIF has been removed.
Tilelink to NASTI/NASTI-Lite bridges are implemented.
All chisel components (Rocket cores, L2 caches) are encapsulated in
a Chisel island with only two NASTI interface exposed.
A NASTI on-chip interconnect (crossbar, buffer, Lite/NASTI bridge)
is provided using SystemVerilog.
UART (Xilinx IP) connected and tested.
SD (Xilinx SPI IP) connected and tested. Software support for FatFS
is provided.
DDR3 RAM and Memory controller (XIlinx IP) is connected and tested.
Bare-metal bootloader: boot from on-chip BRAM, copy a hello
executable from SD to DDR3 RAM and then reset to DDR3 running the hello
executable.
Get rid of the VCS simulation environment and replaced it with
Verilator.
Full Makefile support for FPGA project and FPGA simulation.
TODO:
Modify the RISC-V Linux and port it to the untethered lowRISC SoC.
Currently thinking of revising the Berkeley Bootloader to avoid directly
porting a Linux Kernel.
Best regards,
Wei
7 years, 4 months
Porting tagged memory support to current version of RISC-V Rocket Chip
by Zhe Cheng Lee
Hi, all,
Has anyone successfully port lowRISC changes to support tagged memory to a
more updated version of the rocket chip repository (e.g. develop lowRISC
from a more updated version of the rocket chip repository)?
I want to develop a design module that rely on those tagged memory bits and
are to be integrated with the most recent version of the rocket chip. At
this stage of my development process, I just want at least the L1 caches to
support tagged memory. In other words, I'm not concerned about including
the tag cache or supporting tagged memory in main memory right now. I'm
having trouble successfully pushing the tags into the L1 caches. I have
already added the load/store tag instruction decoding and encoding (I'm
aware that the order of the control signals in the decode table has been
changed a bit since the rocket-chip version lowRISC is based off of), the
new memory access type constant MT_T, and the necessary config parameters.
At first, I thought I just need to include the highlighted modifications in
lowRISC's nbdcache.scala from
https://github.com/lowRISC/rocket/commit/51f65e2dce1bc60ef37c6da956bd8f9c...
and in its tilelink.scala from
https://github.com/lowRISC/uncore/commit/cebfde6d42b7465cab79518fad91e323...
to the corresponding places in rocket-chip's nbdcache.scala, cache.scala,
and tilelink.scala. Even without the tag utilities and tag cache, this
should be fine just for testing existing instructions, since those tag bits
would just be ignored in those cases, correct? But with that, the
simulations do not pass the prebuilt tests and benchmarks that don't test
the load/store tag instructions.
Can anyone help with this?
Thanks.
7 years, 5 months