According to the website, the processor used will be RISC-V 64 bits. I
could not find any mentions about the endianness or other details that I
am interested in. Follows a preamble, doubts at bottom.
In the most recent version of config.sub of autotools , there are
only the strings "riscv32 | riscv64". In config.guess , there's
nothing matching "riscv".
In recent times and for the most popular devices, ARM seems to go mostly
with little endian, but there are also big-endian systems. IBM created
and seems to be investing more effort in ppc64el after having ppc64,
because apparently there is a stronger demand for customers. MIPS have
also mips/mipsel and mips64/mips64el. In these cases (and same for many
other CPUs), they have "registered" the full range of architecture names
in these GNU autotools files, while there is only the aforementioned
"riscv32 | riscv64" for RISC-V, with no "le/el" or "be/eb" attached.
So, my doubts are:
- RISC-V is little-endian in principle, so I guess that the names above
"riscv32 | riscv64" will imply little-endianness, but the ISA manual
says that there can be big or bi-endian variants.
Which one does lowRISC plan to use? And what will be the codename of
the architecture in that case -- "riscv64el/-le", "riscv64eb/-be", or
just plainly "riscv64" (implying little endian)?
- Does lowRISC plan to use different extensions or modifications of
RISC-V, so that the architecture name will be different from
"riscv64*" in any case?
- What would be the architecture triplet name, for GNU toolchain? The
compiler from RISC-V github repositories so far provides:
Maybe some of these questions are not decided yet, or things like naming
in GNU autotools files depend mostly on decisions to be taken by RISC-V
folks rather than people involved in list... But I would be grateful of
any information and pointers that you can provide.
Cheers and thanks in advance.
Manuel A. Fernandez Montecelo <manuel.montezelo(a)gmail.com>